mirror of https://github.com/YosysHQ/yosys.git
abc9_ops: Don't leave unused derived modules lying around
These later become accidentally used for techmap replacements for blackboxes that we don't actually want. Signed-off-by: gatecat <gatecat@ds0.me>
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@ -155,6 +155,9 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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r.first->second = new Design;
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Design *unmap_design = r.first->second;
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// Keep track of derived versions of modules that we haven't used, to prevent these being used for unwanted techmaps later on.
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pool<IdString> unused_derived;
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for (auto module : design->selected_modules())
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for (auto cell : module->cells()) {
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auto inst_module = design->module(cell->type);
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@ -169,6 +172,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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else {
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derived_type = inst_module->derive(design, cell->parameters);
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derived_module = design->module(derived_type);
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unused_derived.insert(derived_type);
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}
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if (derived_module->get_bool_attribute(ID::abc9_flop)) {
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@ -192,6 +196,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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// as a compatible type, yet will be safely unmapped later
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cell->type = derived_type;
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cell->parameters.clear();
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unused_derived.erase(derived_type);
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}
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continue;
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}
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@ -250,7 +255,11 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
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cell->type = derived_type;
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cell->parameters.clear();
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unused_derived.erase(derived_type);
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}
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for (auto unused : unused_derived) {
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design->remove(design->module(unused));
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}
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}
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void prep_bypass(RTLIL::Design *design)
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