mirror of https://github.com/YosysHQ/yosys.git
rmports: Now remove ports from cell instances if we optimized them out of that cell
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0ee27d0226
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@ -43,12 +43,44 @@ struct RmportsPassPass : public Pass {
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{
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log_header(design, "Executing RMPORTS pass (remove top level ports with no connections).\n");
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//The set of ports we removed
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std::map< RTLIL::IdString, std::set<RTLIL::IdString> > removed_ports;
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//Find all of the unused ports, and remove them from that module
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auto modules = design->selected_modules();
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for(auto mod : modules)
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ProcessModule(mod);
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ScanModule(mod, removed_ports);
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//Remove the unused ports from all instances of those modules
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for(auto mod : modules)
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CleanupModule(mod, removed_ports);
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}
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void ProcessModule(RTLIL::Module* module)
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void CleanupModule(RTLIL::Module* module, std::map< RTLIL::IdString, std::set<RTLIL::IdString> >& removed_ports)
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{
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log("Removing now-unused cell ports in module %s\n", module->name.c_str());
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auto cells = module->cells();
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for(auto cell : cells)
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{
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if(removed_ports.find(cell->type) == removed_ports.end())
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{
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//log(" Not touching instance \"%s\" because we didn't remove any ports from module \"%s\"\n",
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// cell->name.c_str(), cell->type.c_str());
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continue;
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}
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auto ports_to_remove = removed_ports[cell->type];
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for(auto p : ports_to_remove)
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{
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log(" Removing port \"%s\" from instance \"%s\"\n",
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p.c_str(), cell->type.c_str());
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cell->unsetPort(p);
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}
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}
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}
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void ScanModule(RTLIL::Module* module, std::map< RTLIL::IdString, std::set<RTLIL::IdString> >& removed_ports)
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{
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log("Finding unconnected ports in module %s\n", module->name.c_str());
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@ -118,6 +150,7 @@ struct RmportsPassPass : public Pass {
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for(auto port : unused_ports)
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{
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log(" removing unused port %s\n", port.c_str());
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removed_ports[module->name].emplace(port);
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//Remove from ports list
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for(size_t i=0; i<module->ports.size(); i++)
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