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Realistic delays for RAM32X1D too

This commit is contained in:
Eddie Hung 2019-06-24 23:05:28 -07:00
parent 3825068a75
commit 158325956e
1 changed files with 2 additions and 2 deletions
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4
techlibs/xilinx/abc_xc7.box
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@ -39,8 +39,8 @@ CARRY4 3 1 10 8
# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
# Outputs: DPO SPO # Outputs: DPO SPO
RAM32X1D 4 0 13 2 RAM32X1D 4 0 13 2
- - - - - - 124 124 124 124 124 - - - - - - - - 631 472 407 238 127 - -
124 124 124 124 124 - - - - - - - - 631 472 407 238 127 - - - - - - - -
# SLICEM/A6LUT # SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE