mirror of https://github.com/YosysHQ/yosys.git
Fixed performance bug in "share" pass
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5a09fa4553
commit
1565d1af69
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@ -793,10 +793,59 @@ struct ShareWorker
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return true;
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return true;
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}
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}
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void optimize_activation_patterns(pool<ssc_pair_t> & /* patterns */)
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void optimize_activation_patterns(pool<ssc_pair_t> &patterns)
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{
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{
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// TODO: Remove patterns that are contained in other patterns
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// TODO: Remove patterns that are contained in other patterns
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// TODO: Consolidate pairs of patterns that only differ in the value for one signal bit
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dict<SigSpec, pool<Const>> db;
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bool did_something = false;
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for (auto const &p : patterns)
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{
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auto &sig = p.first;
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auto &val = p.second;
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int len = GetSize(sig);
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for (int i = 0; i < len; i++)
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{
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auto otherval = val;
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if (otherval.bits[i] == State::S0)
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otherval.bits[i] = State::S1;
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else if (otherval.bits[i] == State::S1)
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otherval.bits[i] = State::S0;
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else
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continue;
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if (db[sig].count(otherval))
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{
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auto newsig = sig;
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newsig.remove(i);
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auto newval = val;
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newval.bits.erase(newval.bits.begin() + i);
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db[newsig].insert(newval);
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db[sig].erase(otherval);
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did_something = true;
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goto next_pattern;
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}
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}
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db[sig].insert(val);
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next_pattern:;
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}
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if (!did_something)
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return;
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patterns.clear();
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for (auto &it : db)
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for (auto &val : it.second)
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patterns.insert(make_pair(it.first, val));
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optimize_activation_patterns(patterns);
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}
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}
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const pool<ssc_pair_t> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent)
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const pool<ssc_pair_t> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent)
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