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Add Xilinx dist RAM as comb boxes

This commit is contained in:
Eddie Hung 2019-06-24 21:54:01 -07:00
parent 49a762ba46
commit 152e682bd5
2 changed files with 16 additions and 0 deletions
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14
techlibs/xilinx/abc_xc7.box
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@ -29,3 +29,17 @@ CARRY4 3 1 10 8
494 465 445 - - 433 469 - - 157 494 465 445 - - 433 469 - - 157
592 540 520 356 - 512 548 292 - 228 592 540 520 356 - 512 548 292 - 228
580 526 507 398 385 508 528 378 380 114 580 526 507 398 385 508 528 378 380 114
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 0 15 2
- - - - - - - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - - - - - - 124 - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 0 17 2
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2
techlibs/xilinx/cells_sim.v
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@ -281,6 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule endmodule
(* abc_box_id = 4, abc_scc_break="D" *)
module RAM64X1D ( module RAM64X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
@ -298,6 +299,7 @@ module RAM64X1D (
always @(posedge clk) if (WE) mem[a] <= D; always @(posedge clk) if (WE) mem[a] <= D;
endmodule endmodule
(* abc_box_id = 5, abc_scc_break="D" *)
module RAM128X1D ( module RAM128X1D (
output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,