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Fix tests -- when Y_WIDTH is non-pow-2

This commit is contained in:
Eddie Hung 2020-01-21 15:02:37 -08:00
parent 8d1b736c4f
commit 152dfd3dd4
1 changed files with 4 additions and 3 deletions
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7
techlibs/common/techmap.v
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@ -150,11 +150,12 @@ module _90_shift_shiftx (A, B, Y);
// Halve the size of $shift/$shiftx by $mux-ing A according to // Halve the size of $shift/$shiftx by $mux-ing A according to
// the LSB of B, after discarding the zeroed bits // the LSB of B, after discarding the zeroed bits
localparam len = 2**(B_WIDTH-1); localparam len = 2**(B_WIDTH-1);
localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
wire [len-1:0] T, F; wire [len-1:0] T, F;
genvar i; genvar i;
for (i = 0; i < A_WIDTH; i=i+Y_WIDTH*2) begin for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
assign F[i/2 +: Y_WIDTH] = A[i +: Y_WIDTH]; assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
assign T[i/2 +: Y_WIDTH] = (i + Y_WIDTH < A_WIDTH) ? A[i+Y_WIDTH +: Y_WIDTH] : {Y_WIDTH{extbit}}; assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}};
end end
wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F; wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F;
wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};