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Fix #1462, #1480.

This commit is contained in:
Marcin Kościelnicki 2019-11-18 08:19:53 +01:00 committed by Marcin Kościelnicki
parent 7a9081440c
commit 15232a48af
4 changed files with 40 additions and 9 deletions
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12
passes/pmgen/xilinx_dsp.pmg
View File

@ -98,16 +98,16 @@ code sigA sigB sigC sigD sigM clock
if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
// Only care about those bits that are used // Only care about those bits that are used
int i; int i;
for (i = 0; i < GetSize(P); i++) { for (i = GetSize(P)-1; i >= 0; i--)
if (nusers(P[i]) <= 1) if (nusers(P[i]) > 1)
break; break;
sigM.append(P[i]); i++;
}
log_assert(nusers(P.extract_end(i)) <= 1); log_assert(nusers(P.extract_end(i)) <= 1);
// This sigM could have no users if downstream sinks (e.g. $add) is // This sigM could have no users if downstream sinks (e.g. $add) is
// narrower than $mul result, for example // narrower than $mul result, for example
if (sigM.empty()) if (i == 0)
reject; reject;
sigM = P.extract(0, i);
} }
else else
sigM = P; sigM = P;
@ -460,6 +460,8 @@ arg argD argQ clock
code code
dff = nullptr; dff = nullptr;
if (GetSize(argQ) == 0)
reject;
for (const auto &c : argQ.chunks()) { for (const auto &c : argQ.chunks()) {
// Abandon matches when 'Q' is a constant // Abandon matches when 'Q' is a constant
if (!c.wire) if (!c.wire)

8
passes/pmgen/xilinx_dsp_CREG.pmg
View File

@ -63,12 +63,12 @@ code sigC sigP clock
if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
// Only care about those bits that are used // Only care about those bits that are used
int i; int i;
for (i = 0; i < GetSize(P); i++) { for (i = GetSize(P)-1; i >= 0; i--)
if (nusers(P[i]) <= 1) if (nusers(P[i]) > 1)
break; break;
sigP.append(P[i]); i++;
}
log_assert(nusers(P.extract_end(i)) <= 1); log_assert(nusers(P.extract_end(i)) <= 1);
sigP = P.extract(0, i);
} }
else else
sigP = P; sigP = P;

11
tests/various/bug1462.ys Normal file
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@ -0,0 +1,11 @@
read_verilog << EOF
module top(...);
input wire [31:0] A;
output wire [31:0] P;
assign P = A * 32'h12300000;
endmodule
EOF
synth_xilinx

18
tests/various/bug1480.ys Normal file
View File

@ -0,0 +1,18 @@
read_verilog << EOF
module top(...);
input signed [17:0] A;
input signed [17:0] B;
output X;
output Y;
wire [35:0] P;
assign P = A * B;
assign X = P[0];
assign Y = P[35];
endmodule
EOF
synth_xilinx