mirror of https://github.com/YosysHQ/yosys.git
Fix missing newline at end of file
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -81,4 +81,4 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
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/* End implementation */
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/* End implementation */
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assign X = AA ^ BB;
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assign X = AA ^ BB;
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endmodule
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endmodule
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