diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index be86f642a..009ba6b97 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1388,8 +1388,12 @@ struct AbcPass : public Pass {
 		log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
 		log("\n");
-		log("This pass does not operate on modules with unprocessed processes in it.\n");
-		log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
+		log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
+		log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
+		log("ABC on logic snippets extracted from your design. You will not get any useful\n");
+		log("output when passing an ABC script that writes a file. Instead write your full\n");
+		log("design as BLIF file with write_blif and the load that into ABC externally if\n");
+		log("you want to use ABC to convert your design into another format.\n");
 		log("\n");
 		log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
 		log("\n");