mirror of https://github.com/YosysHQ/yosys.git
commit
1440f624ee
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@ -1901,3 +1901,14 @@ output OSCOUT;
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parameter FREQ_DIV = 100;
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parameter REGULATOR_EN = 1'b0;
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endmodule
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(* blackbox *)
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module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
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input CLK0, CLK1, CLK2, CLK3, SELFORCE;
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input [3:0] CLKSEL;
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output CLKOUT;
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parameter DCS_MODE = "RISING";
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endmodule
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@ -1564,12 +1564,6 @@ parameter IDLE = 4'd0,
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RD_S2 = 4'd12;
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endmodule
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module DCS (...);
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input CLK0, CLK1, CLK2, CLK3, SELFORCE;
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input [3:0] CLKSEL;
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output CLKOUT;
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endmodule
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module DQCE (...);
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input CLKIN;
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input CE;
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