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remove alu test

This commit is contained in:
Miodrag Milanovic 2019-10-04 10:55:13 +02:00
parent b932654964
commit 1435b9bf97
2 changed files with 0 additions and 36 deletions
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19
tests/anlogic/alu.v
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@ -1,19 +0,0 @@
module top (
input clock,
input [31:0] dinA, dinB,
input [2:0] opcode,
output reg [31:0] dout
);
always @(posedge clock) begin
case (opcode)
0: dout <= dinA + dinB;
1: dout <= dinA - dinB;
2: dout <= dinA >> dinB;
3: dout <= $signed(dinA) >>> dinB;
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
7: dout <= dinA ^ dinB;
endcase
end
endmodule

17
tests/anlogic/alu.ys
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read_verilog alu.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 66 t:AL_MAP_ADDER
select -assert-count 32 t:AL_MAP_LUT1
select -assert-count 23 t:AL_MAP_LUT2
select -assert-count 61 t:AL_MAP_LUT3
select -assert-count 209 t:AL_MAP_LUT4
select -assert-count 100 t:AL_MAP_LUT5
select -assert-count 79 t:AL_MAP_LUT6
select -assert-count 32 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D