From 68b31f5e99e25c6bbd77af3d51c44bef88026c2f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 00:19:58 -0700 Subject: [PATCH 1/4] opt_clean: really make 'clean' identical to 'opt_clean' by rminit too --- passes/opt/opt_clean.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 6271376f1..4e8492f7b 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -611,8 +611,7 @@ struct CleanPass : public Pass { } break; } - if (argidx < args.size()) - extra_args(args, argidx, design); + extra_args(args, argidx, design); keep_cache.reset(design); @@ -627,7 +626,7 @@ struct CleanPass : public Pass { for (auto module : design->selected_whole_modules()) { if (module->has_processes()) continue; - rmunused_module(module, purge_mode, ys_debug(), false); + rmunused_module(module, purge_mode, ys_debug(), true); } log_suppressed(); From fc9fb09a91220602538d99bfd08b1d8c34b69558 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 00:24:23 -0700 Subject: [PATCH 2/4] opt_clean: rminit without -purge; also remove if consistent with const.. warn otherwise --- passes/opt/opt_clean.cc | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4e8492f7b..72ecc30e7 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -412,7 +412,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos return !del_wires_queue.empty(); } -bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) +bool rmunused_module_init(RTLIL::Module *module, bool verbose) { bool did_something = false; CellTypes fftypes; @@ -445,9 +445,6 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) for (auto wire : module->wires()) { - if (!purge_mode && wire->name[0] == '\\') - continue; - if (wire->attributes.count(ID::init) == 0) continue; @@ -464,11 +461,22 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose) if (wire_bit == mapped_wire_bit) goto next_wire; - if (qbits.count(sigmap(SigBit(wire, i))) == 0) - goto next_wire; + if (mapped_wire_bit.wire) { + if (qbits.count(mapped_wire_bit) == 0) + goto next_wire; - if (qbits.at(sigmap(SigBit(wire, i))) != init[i]) - goto next_wire; + if (qbits.at(mapped_wire_bit) != init[i]) + goto next_wire; + } + else { + if (mapped_wire_bit == State::Sx || mapped_wire_bit == State::Sz) + goto next_wire; + + if (mapped_wire_bit != init[i]) { + log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit)); + goto next_wire; + } + } } if (verbose) @@ -512,7 +520,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rmunused_module_cells(module, verbose); while (rmunused_module_signals(module, purge_mode, verbose)) { } - if (rminit && rmunused_module_init(module, purge_mode, verbose)) + if (rminit && rmunused_module_init(module, verbose)) while (rmunused_module_signals(module, purge_mode, verbose)) { } } From aa4a69f89be9fcdcf20ca1c28d67444b994ec479 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 14 May 2020 00:26:23 -0700 Subject: [PATCH 3/4] opt_clean: add init test --- tests/opt/opt_clean_init.ys | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tests/opt/opt_clean_init.ys diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys new file mode 100644 index 000000000..bfc383955 --- /dev/null +++ b/tests/opt/opt_clean_init.ys @@ -0,0 +1,13 @@ +logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1 +logger -expect-no-warnings +read_verilog < Date: Thu, 14 May 2020 00:59:38 -0700 Subject: [PATCH 4/4] opt_clean: improve warning message --- passes/opt/opt_clean.cc | 2 +- tests/opt/opt_clean_init.ys | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 72ecc30e7..f7de02164 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -473,7 +473,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose) goto next_wire; if (mapped_wire_bit != init[i]) { - log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit)); + log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i])); goto next_wire; } } diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys index bfc383955..0d567608d 100644 --- a/tests/opt/opt_clean_init.ys +++ b/tests/opt/opt_clean_init.ys @@ -1,4 +1,4 @@ -logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1 +logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1 logger -expect-no-warnings read_verilog <