mirror of https://github.com/YosysHQ/yosys.git
Undo #895 by instead setting an attribute
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@ -360,23 +360,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
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}
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}
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// Transform into a $shiftx where possible
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if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux") {
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// Create bit-blasted $shiftx-es that shifts by the address line used in the case statement
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auto pmux_b_port = last_mux_cell->getPort("\\B");
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auto pmux_y_port = last_mux_cell->getPort("\\Y");
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int width = last_mux_cell->getParam("\\WIDTH").as_int();
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for (int i = 0; i < width; ++i) {
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RTLIL::SigSpec a_port;
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// Because we went in reverse order above, un-reverse $pmux's B port here
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for (int j = pmux_b_port.size()/width-1; j >= 0; --j)
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a_port.append(pmux_b_port.extract(j*width+i, 1));
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// Create a $shiftx that shifts by the address line used in the case statement
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mod->addShiftx(NEW_ID, a_port, sw->signal, pmux_y_port.extract(i, 1));
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}
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// Disconnect $pmux by replacing its output port with a floating wire
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last_mux_cell->setPort("\\Y", mod->addWire(NEW_ID, width));
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}
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// Mark this pmux as being $shiftx compatible
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if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux")
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last_mux_cell->set_bool_attribute("\\shiftx_compatible");
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}
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return result;
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