mirror of https://github.com/YosysHQ/yosys.git
write_xaiger: be more precise with ff_bits, remove ff_aig_map
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3798fa3bea
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134e70e8e7
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@ -82,7 +82,7 @@ struct XAigerWriter
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<SigBit> ci_bits, co_bits;
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vector<SigBit> ci_bits, co_bits;
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dict<SigBit, std::pair<int,int>> ff_bits;
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dict<SigBit, std::tuple<SigBit,int,int>> ff_bits;
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dict<SigBit, float> arrival_times;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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vector<pair<int, int>> aig_gates;
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@ -242,7 +242,7 @@ struct XAigerWriter
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unused_bits.erase(D);
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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alias_map[Q] = D;
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auto r = ff_bits.insert(std::make_pair(D, std::make_pair(0, 2)));
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auto r = ff_bits.insert(std::make_pair(D, std::make_tuple(Q, 0, 2)));
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log_assert(r.second);
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log_assert(r.second);
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continue;
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continue;
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}
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}
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@ -348,25 +348,26 @@ struct XAigerWriter
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auto it = cell->attributes.find(ID(abc9_mergeability));
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auto it = cell->attributes.find(ID(abc9_mergeability));
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log_assert(it != cell->attributes.end());
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log_assert(it != cell->attributes.end());
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rhs.first = it->second.as_int();
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std::get<1>(rhs) = it->second.as_int();
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cell->attributes.erase(it);
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cell->attributes.erase(it);
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it = cell->attributes.find(ID(abc9_init));
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it = cell->attributes.find(ID(abc9_init));
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log_assert(it != cell->attributes.end());
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log_assert(it != cell->attributes.end());
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log_assert(GetSize(it->second) == 1);
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log_assert(GetSize(it->second) == 1);
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if (it->second[0] == State::S1)
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if (it->second[0] == State::S1)
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rhs.second = 1;
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std::get<2>(rhs) = 1;
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else if (it->second[0] == State::S0)
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else if (it->second[0] == State::S0)
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rhs.second = 0;
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std::get<2>(rhs) = 0;
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else {
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else {
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log_assert(it->second[0] == State::Sx);
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log_assert(it->second[0] == State::Sx);
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rhs.second = 0;
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std::get<2>(rhs) = 0;
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}
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}
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cell->attributes.erase(it);
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cell->attributes.erase(it);
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const SigBit &q = std::get<0>(rhs);
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auto arrival = r.first->second.second;
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auto arrival = r.first->second.second;
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if (arrival)
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if (arrival)
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arrival_times[d] = arrival;
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arrival_times[q] = arrival;
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}
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}
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for (auto &it : bit_users)
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for (auto &it : bit_users)
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@ -510,27 +511,24 @@ struct XAigerWriter
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// pool<> iterates in LIFO order...
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// pool<> iterates in LIFO order...
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for (int i = input_bits.size()-1; i >= 0; i--) {
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for (int i = input_bits.size()-1; i >= 0; i--) {
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const auto &bit = *input_bits.element(i);
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const auto &bit = *input_bits.element(i);
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log_dump(bit, i);
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aig_m++, aig_i++;
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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aig_map[bit] = 2*aig_m;
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}
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}
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for (const auto &i : ff_bits) {
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for (const auto &i : ff_bits) {
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const SigBit &bit = i.first;
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const SigBit &q = std::get<0>(i.second);
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aig_m++, aig_i++;
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log_assert(!aig_map.count(q));
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aig_map[q] = 2*aig_m;
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}
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for (auto &bit : ci_bits) {
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aig_m++, aig_i++;
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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aig_map[bit] = 2*aig_m;
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}
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}
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dict<SigBit, int> ff_aig_map;
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for (auto &bit : ci_bits) {
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aig_m++, aig_i++;
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auto r = aig_map.insert(std::make_pair(bit, 2*aig_m));
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if (!r.second)
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ff_aig_map[bit] = 2*aig_m;
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}
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for (auto bit : co_bits) {
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for (auto bit : co_bits) {
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ordered_outputs[bit] = aig_o++;
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ordered_outputs[bit] = aig_o++;
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aig_outputs.push_back(bit2aig(bit));
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aig_outputs.push_back(bit2aig(bit));
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@ -544,9 +542,9 @@ struct XAigerWriter
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}
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}
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for (auto &i : ff_bits) {
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for (auto &i : ff_bits) {
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const SigBit &bit = i.first;
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const SigBit &d = i.first;
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aig_o++;
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aig_o++;
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aig_outputs.push_back(ff_aig_map.at(bit));
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aig_outputs.push_back(aig_map.at(d));
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}
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}
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}
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}
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@ -752,13 +750,13 @@ struct XAigerWriter
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write_s_buffer(ff_bits.size());
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write_s_buffer(ff_bits.size());
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for (const auto &i : ff_bits) {
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for (const auto &i : ff_bits) {
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const SigBit &bit = i.first;
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const SigBit &q = std::get<0>(i.second);
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int mergeability = i.second.first;
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int mergeability = std::get<1>(i.second);
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log_assert(mergeability > 0);
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log_assert(mergeability > 0);
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write_r_buffer(mergeability);
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write_r_buffer(mergeability);
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int init = i.second.second;
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int init = std::get<2>(i.second);
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write_s_buffer(init);
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write_s_buffer(init);
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write_i_buffer(arrival_times.at(bit, 0));
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write_i_buffer(arrival_times.at(q, 0));
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//write_o_buffer(0);
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//write_o_buffer(0);
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}
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}
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