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Fixed parsing of verilog macros at end of line

This commit is contained in:
Clifford Wolf 2014-01-18 19:22:20 +01:00
parent 2fbaaaca7a
commit 13359d65ba
1 changed files with 1 additions and 1 deletions
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2
frontends/verilog/preproc.cc
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@ -386,7 +386,7 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
std::string name = tok.substr(1); std::string name = tok.substr(1);
// printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str()); // printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str());
std::string skipped_spaces = skip_spaces(); std::string skipped_spaces = skip_spaces();
tok = next_token(true); tok = next_token(false);
if (tok == "(" && defines_with_args.count(name) > 0) { if (tok == "(" && defines_with_args.count(name) > 0) {
int level = 1; int level = 1;
std::vector<std::string> args; std::vector<std::string> args;