mirror of https://github.com/YosysHQ/yosys.git
Re-enabled assert for new logic loops in "share" pass
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@ -1055,10 +1055,7 @@ struct ShareWorker
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log_assert(recursion_state.empty());
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log_assert(recursion_state.empty());
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bool after_scc = before_scc || module_has_scc();
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bool after_scc = before_scc || module_has_scc();
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if (before_scc != after_scc)
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log_assert(before_scc == after_scc);
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log("Warning: introduced topological logic loops!\n");
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// Pass::call_on_module(design, module, "scc;; show");
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// log_assert(before_scc == after_scc);
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}
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}
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};
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};
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