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Merge pull request #3419 from jix/sim_nested_anyseq 

sim: Fix $anyseq in nested modules
This commit is contained in:
Jannis Harder 2022-07-22 15:41:41 +02:00 committed by GitHub
parent a82eff2e20 14ba50908b
commit 12b0ce9721
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 21 additions and 11 deletions
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32
passes/sat/sim.cc
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@ -157,6 +157,7 @@ struct SimInstance
dict<Wire*, pair<int, Const>> signal_database; dict<Wire*, pair<int, Const>> signal_database;
dict<Wire*, fstHandle> fst_handles; dict<Wire*, fstHandle> fst_handles;
dict<Wire*, fstHandle> fst_inputs;
dict<IdString, dict<int,fstHandle>> fst_memories; dict<IdString, dict<int,fstHandle>> fst_memories;
SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) : SimInstance(SimShared *shared, std::string scope, Module *module, Cell *instance = nullptr, SimInstance *parent = nullptr) :
@ -820,7 +821,7 @@ struct SimInstance
return did_something; return did_something;
} }
void addAdditionalInputs(std::map<Wire*,fstHandle> &inputs) void addAdditionalInputs()
{ {
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
@ -831,7 +832,7 @@ struct SimInstance
for(auto &item : fst_handles) { for(auto &item : fst_handles) {
if (item.second==0) continue; // Ignore signals not found if (item.second==0) continue; // Ignore signals not found
if (sig_y == sigmap(item.first)) { if (sig_y == sigmap(item.first)) {
inputs[sig_y.as_wire()] = item.second; fst_inputs[sig_y.as_wire()] = item.second;
found = true; found = true;
break; break;
} }
@ -842,7 +843,21 @@ struct SimInstance
} }
} }
for (auto child : children) for (auto child : children)
child.second->addAdditionalInputs(inputs); child.second->addAdditionalInputs();
}
bool setInputs()
{
bool did_something = false;
for(auto &item : fst_inputs) {
std::string v = shared->fst->valueOf(item.second);
did_something |= set_state(item.first, Const::from_string(v));
}
for (auto child : children)
did_something |= child.second->setInputs();
return did_something;
} }
void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values) void setState(dict<int, std::pair<SigBit,bool>> bits, std::string values)
@ -1095,18 +1110,17 @@ struct SimWorker : SimShared
} }
SigMap sigmap(topmod); SigMap sigmap(topmod);
std::map<Wire*,fstHandle> inputs;
for (auto wire : topmod->wires()) { for (auto wire : topmod->wires()) {
if (wire->port_input) { if (wire->port_input) {
fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); fstHandle id = fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0) if (id==0)
log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str()); log_error("Unable to find required '%s' signal in file\n",(scope + "." + RTLIL::unescape_id(wire->name)).c_str());
inputs[wire] = id; top->fst_inputs[wire] = id;
} }
} }
top->addAdditionalInputs(inputs); top->addAdditionalInputs();
uint64_t startCount = 0; uint64_t startCount = 0;
uint64_t stopCount = 0; uint64_t stopCount = 0;
@ -1152,11 +1166,7 @@ struct SimWorker : SimShared
fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) { fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
if (verbose) if (verbose)
log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString()); log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
bool did_something = false; bool did_something = top->setInputs();
for(auto &item : inputs) {
std::string v = fst->valueOf(item.second);
did_something |= top->set_state(item.first, Const::from_string(v));
}
if (initial) { if (initial) {
did_something |= top->setInitState(); did_something |= top->setInitState();