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Merge pull request #4020 from YosysHQ/revert-4019-lofty/abc9-by-default 

Revert "ice40, ecp5: enable ABC9 by default"
This commit is contained in:
Lofty 2023-11-03 14:53:15 +00:00 committed by GitHub
parent deebb82e85 b8b47f7c6c
commit 1260766d91
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GPG Key ID: 4AEE18F83AFDEB23
6 changed files with 16 additions and 28 deletions
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12
techlibs/ecp5/synth_ecp5.cc
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@ -93,8 +93,8 @@ struct SynthEcp5Pass : public ScriptPass
log(" -abc2\n");
log(" run two passes of 'abc' for slightly improved logic density\n");
log("\n");
log(" -noabc9\n");
log(" disable use of new ABC9 flow\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log(" -vpr\n");
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
@ -137,7 +137,7 @@ struct SynthEcp5Pass : public ScriptPass
retime = false;
abc2 = false;
vpr = false;
abc9 = true;
abc9 = false;
iopad = false;
nodsp = false;
no_rw_check = false;
@ -224,11 +224,7 @@ struct SynthEcp5Pass : public ScriptPass
continue;
}
if (args[argidx] == "-abc9") {
// removed, ABC9 is on by default.
continue;
}
if (args[argidx] == "-noabc9") {
abc9 = false;
abc9 = true;
continue;
}
if (args[argidx] == "-iopad") {

12
techlibs/ice40/synth_ice40.cc
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@ -106,8 +106,8 @@ struct SynthIce40Pass : public ScriptPass
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
log(" -noabc9\n");
log(" disable use of new ABC9 flow\n");
log(" -abc9\n");
log(" use new ABC9 flow (EXPERIMENTAL)\n");
log("\n");
log(" -flowmap\n");
log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n");
@ -144,7 +144,7 @@ struct SynthIce40Pass : public ScriptPass
noabc = false;
abc2 = false;
vpr = false;
abc9 = true;
abc9 = false;
flowmap = false;
device_opt = "hx";
no_rw_check = false;
@ -235,11 +235,7 @@ struct SynthIce40Pass : public ScriptPass
continue;
}
if (args[argidx] == "-abc9") {
// removed, ABC9 is on by default.
continue;
}
if (args[argidx] == "-noabc9") {
abc9 = false;
abc9 = true;
continue;
}
if (args[argidx] == "-dff") {

7
tests/arch/ecp5/add_sub.ys
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@ -4,9 +4,6 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-min 25 t:LUT4
select -assert-max 26 t:LUT4
select -assert-count 10 t:PFUMX
select -assert-count 6 t:L6MUX21
select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D
select -assert-count 10 t:LUT4
select -assert-none t:LUT4 %% t:* %D

3
tests/arch/ecp5/counter.ys
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@ -5,7 +5,6 @@ flatten
equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4
select -assert-count 4 t:CCU2C
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:CCU2C t:TRELLIS_FF %% t:* %D
select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D

2
tests/arch/ice40/add_sub.ys
View File

@ -3,7 +3,7 @@ hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:SB_LUT4
select -assert-count 11 t:SB_LUT4
select -assert-count 6 t:SB_CARRY
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D

8
tests/arch/ice40/mux.ys
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@ -15,7 +15,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:SB_LUT4
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
@ -25,7 +25,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 6 t:SB_LUT4
select -assert-count 5 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
@ -35,7 +35,7 @@ proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-min 13 t:SB_LUT4
select -assert-max 14 t:SB_LUT4
select -assert-min 11 t:SB_LUT4
select -assert-max 12 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D