riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix typo.

This commit is contained in:
whitequark 2018-12-05 04:32:01 +00:00
parent e115303129
commit 12596b5003
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/common/simcells.v
View File

@ -465,7 +465,7 @@ endmodule
//- //-
//- $_SR_NP_ (S, R, Q) //- $_SR_NP_ (S, R, Q)
//- //-
//- A set-reset latch with negative polarity SET and positive polarioty RESET. //- A set-reset latch with negative polarity SET and positive polarity RESET.
//- //-
//- Truth table: S R | Q //- Truth table: S R | Q
//- -----+--- //- -----+---
@ -489,7 +489,7 @@ endmodule
//- //-
//- $_SR_PN_ (S, R, Q) //- $_SR_PN_ (S, R, Q)
//- //-
//- A set-reset latch with positive polarity SET and negative polarioty RESET. //- A set-reset latch with positive polarity SET and negative polarity RESET.
//- //-
//- Truth table: S R | Q //- Truth table: S R | Q
//- -----+--- //- -----+---