mirror of https://github.com/YosysHQ/yosys.git
Added techmap_wrap attribute
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b34ca15185
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124e759280
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@ -349,22 +349,26 @@ struct TechmapWorker
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if (tpl->get_bool_attribute("\\techmap_maccmap"))
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if (tpl->get_bool_attribute("\\techmap_maccmap"))
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extmapper_name = "maccmap";
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extmapper_name = "maccmap";
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if (tpl->attributes.count("\\techmap_wrap"))
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extmapper_name = "wrap";
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if (!extmapper_name.empty())
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if (!extmapper_name.empty())
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{
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{
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cell->type = cell_type;
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cell->type = cell_type;
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if (extern_mode && !in_recursion)
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if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
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{
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{
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std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
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std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
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for (auto &c : cell->parameters)
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for (auto &c : cell->parameters)
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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RTLIL::Module *extmapper_module = design->module(m_name);
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RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
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RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
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if (extmapper_module == nullptr)
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if (extmapper_module == nullptr)
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{
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{
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extmapper_module = design->addModule(m_name);
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extmapper_module = extmapper_design->addModule(m_name);
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RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
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RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
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int port_counter = 1;
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int port_counter = 1;
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@ -378,6 +382,7 @@ struct TechmapWorker
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c.second = w;
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c.second = w;
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}
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}
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extmapper_module->fixup_ports();
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extmapper_module->check();
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extmapper_module->check();
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if (extmapper_name == "simplemap") {
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if (extmapper_name == "simplemap") {
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@ -385,6 +390,7 @@ struct TechmapWorker
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if (simplemap_mappers.count(extmapper_cell->type) == 0)
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if (simplemap_mappers.count(extmapper_cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
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log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
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simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
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simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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}
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if (extmapper_name == "maccmap") {
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if (extmapper_name == "maccmap") {
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@ -392,14 +398,26 @@ struct TechmapWorker
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if (extmapper_cell->type != "$macc")
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if (extmapper_cell->type != "$macc")
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log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
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log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
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maccmap(extmapper_module, extmapper_cell);
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maccmap(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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}
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extmapper_module->remove(extmapper_cell);
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if (extmapper_name == "wrap") {
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std::string cmd_string = tpl->attributes.at("\\techmap_wrap").decode_string();
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log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
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Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
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log_continue = true;
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}
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}
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cell->type = extmapper_module->name;
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cell->parameters.clear();
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if (!extern_mode || in_recursion) {
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tpl = extmapper_module;
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goto use_wrapper_tpl;
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}
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}
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log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
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log("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
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cell->type = extmapper_module->name;
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cell->parameters.clear();
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}
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}
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else
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else
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{
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{
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@ -426,6 +444,7 @@ struct TechmapWorker
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break;
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break;
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}
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}
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use_wrapper_tpl:
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for (auto conn : cell->connections()) {
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for (auto conn : cell->connections()) {
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if (conn.first.substr(0, 1) == "$")
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if (conn.first.substr(0, 1) == "$")
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continue;
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continue;
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@ -786,6 +805,10 @@ struct TechmapPass : public Pass {
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log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
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log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
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log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
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log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
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log("\n");
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log("\n");
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log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
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log("will create a wrapper for the cell and then run the command string that the\n");
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log("attribute is set to on the wrapper module.\n");
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log("\n");
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log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
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log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
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log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
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log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
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log("the mapping module to the techmap command. At the moment the following special\n");
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log("the mapping module to the techmap command. At the moment the following special\n");
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