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Common memory test now shared

This commit is contained in:
Miodrag Milanovic 2019-10-18 12:33:35 +02:00
parent 477702b8c9
commit 12383f37b2
10 changed files with 5 additions and 89 deletions
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2
tests/arch/anlogic/memory.ys
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@ -1,4 +1,4 @@
read_verilog memory.v read_verilog ../common/memory.v
hierarchy -top top hierarchy -top top
proc proc
memory -nomap memory -nomap

0
tests/arch/anlogic/memory.v → tests/arch/common/memory.v
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21
tests/arch/ecp5/memory.v
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@ -1,21 +0,0 @@
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule

2
tests/arch/ecp5/memory.ys
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@ -1,4 +1,4 @@
read_verilog memory.v read_verilog ../common/memory.v
hierarchy -top top hierarchy -top top
proc proc
memory -nomap memory -nomap

21
tests/arch/efinix/memory.v
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@ -1,21 +0,0 @@
module top
(
input [7:0] data_a,
input [8:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule

2
tests/arch/efinix/memory.ys
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@ -1,4 +1,4 @@
read_verilog memory.v read_verilog ../common/memory.v
hierarchy -top top hierarchy -top top
proc proc
memory -nomap memory -nomap

21
tests/arch/ice40/memory.v
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@ -1,21 +0,0 @@
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule

2
tests/arch/ice40/memory.ys
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@ -1,4 +1,4 @@
read_verilog memory.v read_verilog ../common/memory.v
hierarchy -top top hierarchy -top top
proc proc
memory -nomap memory -nomap

21
tests/arch/xilinx/memory.v
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@ -1,21 +0,0 @@
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule

2
tests/arch/xilinx/memory.ys
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@ -1,4 +1,4 @@
read_verilog memory.v read_verilog ../common/memory.v
hierarchy -top top hierarchy -top top
proc proc
memory -nomap memory -nomap