mirror of https://github.com/YosysHQ/yosys.git
read_verilog: don't include empty `opt_sva_label` in span.
Consider this SystemVerilog file: module top(...); input clk; input [7:0] data; input ack; always @(posedge clk) if (ack) begin assert(data != 8'h0a); end endmodule Before this commit, the span for the assert was: if (ack) begin> assert(data != 8'h0a)<; After this commit, the span for the assert is: if (ack) begin >assert(data != 8'h0a)<; This helps editor integrations that only look at the beginning of the span.
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@ -2484,7 +2484,7 @@ assert:
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delete $5;
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} else {
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AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
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SET_AST_NODE_LOC(node, @1, @6);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
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if ($1 != nullptr)
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node->str = *$1;
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ast_stack.back()->children.push_back(node);
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@ -2497,7 +2497,7 @@ assert:
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delete $5;
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} else {
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AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
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SET_AST_NODE_LOC(node, @1, @6);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
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if ($1 != nullptr)
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node->str = *$1;
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ast_stack.back()->children.push_back(node);
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@ -2510,7 +2510,7 @@ assert:
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delete $6;
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} else {
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AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
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SET_AST_NODE_LOC(node, @1, @7);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7);
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if ($1 != nullptr)
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node->str = *$1;
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ast_stack.back()->children.push_back(node);
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@ -2523,7 +2523,7 @@ assert:
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delete $6;
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} else {
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AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
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SET_AST_NODE_LOC(node, @1, @7);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7);
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if ($1 != nullptr)
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node->str = *$1;
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ast_stack.back()->children.push_back(node);
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@ -2533,7 +2533,7 @@ assert:
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} |
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opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
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AstNode *node = new AstNode(AST_COVER, $5);
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SET_AST_NODE_LOC(node, @1, @6);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
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if ($1 != nullptr) {
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node->str = *$1;
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delete $1;
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@ -2542,7 +2542,7 @@ assert:
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} |
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opt_sva_label TOK_COVER opt_property '(' ')' ';' {
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AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
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SET_AST_NODE_LOC(node, @1, @5);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @5);
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if ($1 != nullptr) {
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node->str = *$1;
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delete $1;
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@ -2551,7 +2551,7 @@ assert:
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} |
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opt_sva_label TOK_COVER ';' {
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AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
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SET_AST_NODE_LOC(node, @1, @2);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @2);
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if ($1 != nullptr) {
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node->str = *$1;
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delete $1;
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@ -2563,7 +2563,7 @@ assert:
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delete $5;
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} else {
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AstNode *node = new AstNode(AST_ASSUME, $5);
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SET_AST_NODE_LOC(node, @1, @6);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @6);
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if ($1 != nullptr)
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node->str = *$1;
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ast_stack.back()->children.push_back(node);
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@ -2578,7 +2578,7 @@ assert:
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delete $6;
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} else {
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AstNode *node = new AstNode(AST_FAIR, $6);
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SET_AST_NODE_LOC(node, @1, @7);
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SET_AST_NODE_LOC(node, ($1 != nullptr ? @1 : @2), @7);
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if ($1 != nullptr)
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node->str = *$1;
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ast_stack.back()->children.push_back(node);
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