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Fixed sat handling of $eqx and $nex with unequal port widths

This commit is contained in:
Clifford Wolf 2013-12-27 18:11:05 +01:00
parent 1dcbba1abf
commit 122b3c067b
1 changed files with 2 additions and 0 deletions
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2
kernel/satgen.h
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@ -462,6 +462,7 @@ struct SatGen
if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) { if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
a = ez->vec_or(a, undef_a); a = ez->vec_or(a, undef_a);
b = ez->vec_or(b, undef_b); b = ez->vec_or(b, undef_b);
} }
@ -486,6 +487,7 @@ struct SatGen
std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
if (cell->type == "$eqx") if (cell->type == "$eqx")
yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b)); yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b));