riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix typo

This commit is contained in:
Eddie Hung 2019-09-27 17:00:19 -07:00
parent 8f5710c464
commit 11cb5fab00
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
kernel/rtlil.cc
View File

@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
{
std::vector<RTLIL::Cell*> result;
result.reserve(wires_.size());
result.reserve(cells_.size());
for (auto &it : cells_)
if (design->selected(this, it.second))
result.push_back(it.second);