mirror of https://github.com/YosysHQ/yosys.git
Performance improvements in freduce pass
This commit is contained in:
Clifford Wolf
parent
c44e1bec6d
commit
10f45b8c8e
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@ -59,12 +59,10 @@ struct CountBitUsage
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CountBitUsage(SigMap &sigmap, std::map<RTLIL::SigBit, int> &cache) : sigmap(sigmap), cache(cache) { }
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void operator()(RTLIL::SigSpec &sig)
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{
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void operator()(RTLIL::SigSpec &sig) {
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std::vector<RTLIL::SigBit> vec = sigmap(sig).to_sigbit_vector();
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for (auto &bit : vec) {
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log("%s %d\n", log_signal(bit), cache[bit]++);
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}
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for (auto &bit : vec)
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cache[bit]++;
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}
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};
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@ -116,10 +114,10 @@ struct FindReducedInputs
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pi.insert(pi.end(), pi_set.begin(), pi_set.end());
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}
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void analyze(std::vector<RTLIL::SigBit> &reduced_inputs, RTLIL::SigBit output)
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void analyze(std::vector<RTLIL::SigBit> &reduced_inputs, RTLIL::SigBit output, int prec)
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{
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if (verbose_level >= 1)
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log(" Analyzing input cone for signal %s:\n", log_signal(output));
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log("[%2d%%] Analyzing input cone for signal %s:\n", prec, log_signal(output));
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std::vector<RTLIL::SigBit> pi;
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register_cone(pi, output);
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@ -235,25 +233,28 @@ struct PerformReduction
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out_inverted = std::vector<bool>(sat_out.size(), false);
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}
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void analyze(std::vector<std::set<int>> &results, std::map<int, int> &results_map, std::vector<int> &bucket, int level)
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void analyze(std::vector<std::set<int>> &results, std::map<int, int> &results_map, std::vector<int> &bucket, std::string indent1, std::string indent2)
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{
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std::string indent = indent1 + indent2;
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const char *indt = indent.c_str();
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if (bucket.size() <= 1)
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return;
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if (verbose_level == 1)
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log("%*s Trying to shatter bucket with %d signals.\n", 2*level, "", int(bucket.size()));
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log("%s Trying to shatter bucket with %d signals.\n", indt, int(bucket.size()));
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if (verbose_level > 1) {
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std::vector<RTLIL::SigBit> bucket_sigbits;
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for (int idx : bucket)
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bucket_sigbits.push_back(out_bits[idx]);
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log("%*s Trying to shatter bucket with %d signals: %s\n", 2*level, "", int(bucket.size()), log_signal(RTLIL::SigSpec(bucket_sigbits).optimized()));
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log("%s Trying to shatter bucket with %d signals: %s\n", indt, int(bucket.size()), log_signal(RTLIL::SigSpec(bucket_sigbits).optimized()));
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}
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std::vector<int> sat_list, sat_inv_list;
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std::vector<int> sat_set_list, sat_clr_list;
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for (int idx : bucket) {
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sat_list.push_back(ez.AND(sat_out[idx], sat_def[idx]));
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sat_inv_list.push_back(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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sat_set_list.push_back(ez.AND(sat_out[idx], sat_def[idx]));
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sat_clr_list.push_back(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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}
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std::vector<int> modelVars = sat_out;
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@ -263,13 +264,47 @@ struct PerformReduction
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if (verbose_level >= 2)
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modelVars.insert(modelVars.end(), sat_pi.begin(), sat_pi.end());
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if (ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_list), ez.expression(ezSAT::OpOr, sat_inv_list)))
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if (ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_set_list), ez.expression(ezSAT::OpOr, sat_clr_list)))
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{
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int iter_count = 1;
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while (1)
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{
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sat_set_list.clear();
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sat_clr_list.clear();
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std::vector<int> sat_def_list;
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for (int idx : bucket)
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if (!model[sat_out.size() + idx]) {
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sat_set_list.push_back(ez.AND(sat_out[idx], sat_def[idx]));
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sat_clr_list.push_back(ez.AND(ez.NOT(sat_out[idx]), sat_def[idx]));
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} else {
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sat_def_list.push_back(sat_def[idx]);
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}
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if (!ez.solve(modelVars, model, ez.expression(ezSAT::OpOr, sat_set_list), ez.expression(ezSAT::OpOr, sat_clr_list), ez.expression(ezSAT::OpAnd, sat_def_list)))
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break;
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iter_count++;
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}
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if (verbose_level >= 1) {
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int count_set = 0, count_clr = 0, count_undef = 0;
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for (int idx : bucket)
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if (!model[sat_out.size() + idx])
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count_undef++;
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else if (model[idx])
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count_set++;
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else
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count_clr++;
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log("%s After %d iterations: %d set vs. %d clr vs %d undef\n", indt, iter_count, count_set, count_clr, count_undef);
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}
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if (verbose_level >= 2) {
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for (size_t i = 0; i < pi_bits.size(); i++)
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log("%*s -> PI %c == %s\n", 2*level, "", model[2*sat_out.size() + i] ? '1' : '0', log_signal(pi_bits[i]));
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log("%s -> PI %c == %s\n", indt, model[2*sat_out.size() + i] ? '1' : '0', log_signal(pi_bits[i]));
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for (int idx : bucket)
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log("%*s -> OUT %c == %s%s\n", 2*level, "", model[sat_out.size() + idx] ? model[idx] ? '1' : '0' : 'x',
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log("%s -> OUT %c == %s%s\n", indt, model[sat_out.size() + idx] ? model[idx] ? '1' : '0' : 'x',
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out_inverted.at(idx) ? "~" : "", log_signal(out_bits[idx]));
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}
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@ -282,8 +317,8 @@ struct PerformReduction
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if (!model[sat_out.size() + idx] || !model[idx])
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buckets_b.push_back(idx);
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}
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analyze(results, results_map, buckets_a, level+1);
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analyze(results, results_map, buckets_b, level+1);
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analyze(results, results_map, buckets_a, indent1 + ".", indent2 + " ");
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analyze(results, results_map, buckets_b, indent1 + "x", indent2 + " ");
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}
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else
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{
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@ -300,7 +335,7 @@ struct PerformReduction
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if (undef_slaves.size() == bucket.size()) {
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if (verbose_level >= 1)
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log("%*s Complex undef overlap. None of the signals covers the others.\n", 2*level, "");
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log("%s Complex undef overlap. None of the signals covers the others.\n", indt);
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// FIXME: We could try to further shatter a group with complex undef overlaps
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return;
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}
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@ -309,7 +344,7 @@ struct PerformReduction
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out_depth[idx] = std::numeric_limits<int>::max();
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if (verbose_level >= 1) {
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log("%*s Found %d equivialent signals:", 2*level, "", int(bucket.size()));
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log("%s Found %d equivialent signals:", indt, int(bucket.size()));
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for (int idx : bucket)
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log("%s%s%s", idx == bucket.front() ? " " : ", ", out_inverted[idx] ? "~" : "", log_signal(out_bits[idx]));
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log("\n");
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@ -347,7 +382,7 @@ struct PerformReduction
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std::vector<std::set<int>> results_buf;
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std::map<int, int> results_map;
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analyze(results_buf, results_map, bucket, 1);
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analyze(results_buf, results_map, bucket, "", "");
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for (auto &r : results_buf)
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{
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@ -432,10 +467,13 @@ struct FreduceWorker
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ct.setup_internals();
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ct.setup_stdcells();
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int bits_full_total = 0;
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std::vector<std::set<RTLIL::SigBit>> batches;
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for (auto &it : module->wires)
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if (it.second->port_input)
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if (it.second->port_input) {
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batches.push_back(sigmap(it.second).to_sigbit_set());
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bits_full_total += it.second->width;
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}
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for (auto &it : module->cells) {
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if (ct.cell_known(it.second->type)) {
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std::set<RTLIL::SigBit> inputs, outputs;
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@ -450,18 +488,21 @@ struct FreduceWorker
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for (auto &bit : outputs)
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drivers[bit] = drv;
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batches.push_back(outputs);
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bits_full_total += outputs.size();
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}
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if (inv_mode && it.second->type == "$_INV_")
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inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->connections.at("\\A")), sigmap(it.second->connections.at("\\Y"))));
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}
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int bits_count = 0;
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int bits_full_count = 0;
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std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets;
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for (auto &batch : batches)
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{
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for (auto &bit : batch)
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if (bit.wire != NULL && design->selected(module, bit.wire))
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goto found_selected_wire;
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bits_full_count += batch.size();
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continue;
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found_selected_wire:
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@ -471,8 +512,9 @@ struct FreduceWorker
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FindReducedInputs infinder(sigmap, drivers);
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for (auto &bit : batch) {
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std::vector<RTLIL::SigBit> inputs;
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infinder.analyze(inputs, bit);
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infinder.analyze(inputs, bit, 100 * bits_full_count / bits_full_total);
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buckets[inputs].push_back(bit);
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bits_full_count++;
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bits_count++;
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}
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}
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