Refactoring: Renamed RTLIL::Design::modules to modules_

backends/autotest/autotest.cc

@@ -91,7 +91,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
 	fprintf(f, "end\n");
 	fprintf(f, "endtask\n\n");
 
-	for (auto it = design->modules.begin(); it != design->modules.end(); it++)
+	for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
 	{
 		std::map<std::string, int> signal_in;
 		std::map<std::string, std::string> signal_const;
@@ -292,7 +292,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
 	fprintf(f, "initial begin\n");
 	fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n");
 	fprintf(f, "\t// $dumpvars(0, testbench);\n");
-	for (auto it = design->modules.begin(); it != design->modules.end(); it++)
+	for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
 		if (!it->second->get_bool_attribute("\\gentb_skip"))
 			fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
 	fprintf(f, "\t$finish;\n");

backends/blif/blif.cc

@@ -89,9 +89,9 @@ struct BlifDumper
 	{
 		if (!config->gates_mode)
 			return "subckt";
-		if (!design->modules.count(RTLIL::escape_id(cell_type)))
+		if (!design->modules_.count(RTLIL::escape_id(cell_type)))
 			return "gate";
-		if (design->modules.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
+		if (design->modules_.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
 			return "gate";
 		return "subckt";
 	}
@@ -362,7 +362,7 @@ struct BlifBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules)
+			for (auto & mod_it:design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_module_name = mod_it.first;
 
@@ -370,7 +370,7 @@ struct BlifBackend : public Backend {
 
 		std::vector<RTLIL::Module*> mod_list;
 
-		for (auto module_it : design->modules)
+		for (auto module_it : design->modules_)
 		{
 			RTLIL::Module *module = module_it.second;
 			if (module->get_bool_attribute("\\blackbox"))

backends/btor/btor.cc

@@ -964,7 +964,7 @@ struct BtorBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 		
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules)
+			for (auto & mod_it:design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_module_name = mod_it.first;
 
@@ -975,7 +975,7 @@ struct BtorBackend : public Backend {
 		
 		std::vector<RTLIL::Module*> mod_list;
 
-		for (auto module_it : design->modules)
+		for (auto module_it : design->modules_)
 		{
 			RTLIL::Module *module = module_it.second;
 			if (module->get_bool_attribute("\\blackbox"))

backends/edif/edif.cc

@@ -125,11 +125,11 @@ struct EdifBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules)
+			for (auto & mod_it:design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_module_name = mod_it.first;
 
-		for (auto module_it : design->modules)
+		for (auto module_it : design->modules_)
 		{
 			RTLIL::Module *module = module_it.second;
 			if (module->get_bool_attribute("\\blackbox"))
@@ -146,7 +146,7 @@ struct EdifBackend : public Backend {
 			for (auto cell_it : module->cells_)
 			{
 				RTLIL::Cell *cell = cell_it.second;
-				if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
+				if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
 					lib_cell_ports[cell->type];
 					for (auto p : cell->connections()) {
 						if (p.second.size() > 1)
@@ -213,11 +213,11 @@ struct EdifBackend : public Backend {
 
 		// extract module dependencies
 		std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			module_deps[mod_it.second] = std::set<RTLIL::Module*>();
 			for (auto &cell_it : mod_it.second->cells_)
-				if (design->modules.count(cell_it.second->type) > 0)
+				if (design->modules_.count(cell_it.second->type) > 0)
-					module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
+					module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
 		}
 
 		// simple good-enough topological sort

backends/ilang/ilang_backend.cc

@@ -339,7 +339,7 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_
 
 	if (!flag_m) {
 		int count_selected_mods = 0;
-		for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+		for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
 			if (design->selected_whole_module(it->first))
 				flag_m = true;
 			if (design->selected(it->second))
@@ -355,7 +355,7 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_
 		fprintf(f, "autoidx %d\n", RTLIL::autoidx);
 	}
 
-	for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+	for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
 		if (!only_selected || design->selected(it->second)) {
 			if (only_selected)
 				fprintf(f, "\n");

backends/intersynth/intersynth.cc

@@ -121,7 +121,7 @@ struct IntersynthBackend : public Backend {
 		for (auto lib : libs)
 			ct.setup_design(lib);
 
-		for (auto module_it : design->modules)
+		for (auto module_it : design->modules_)
 		{
 			RTLIL::Module *module = module_it.second;
 			SigMap sigmap(module);

backends/spice/spice.cc

@@ -54,7 +54,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 
 		std::vector<RTLIL::SigSpec> port_sigs;
 
-		if (design->modules.count(cell->type) == 0)
+		if (design->modules_.count(cell->type) == 0)
 		{
 			log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
 					RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
@@ -65,7 +65,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 		}
 		else
 		{
-			RTLIL::Module *mod = design->modules.at(cell->type);
+			RTLIL::Module *mod = design->modules_.at(cell->type);
 
 			std::vector<RTLIL::Wire*> ports;
 			for (auto wire_it : mod->wires_) {
@@ -171,14 +171,14 @@ struct SpiceBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		if (top_module_name.empty())
-			for (auto & mod_it:design->modules)
+			for (auto & mod_it:design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_module_name = mod_it.first;
 
 		fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
 		fprintf(f, "\n");
 
-		for (auto module_it : design->modules)
+		for (auto module_it : design->modules_)
 		{
 			RTLIL::Module *module = module_it.second;
 			if (module->get_bool_attribute("\\blackbox"))

backends/verilog/verilog_backend.cc

@@ -1055,7 +1055,7 @@ struct VerilogBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		fprintf(f, "/* Generated by %s */\n", yosys_version_str);
-		for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+		for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
 			if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
 				continue;
 			if (selected && !design->selected_whole_module(it->first)) {

frontends/ast/ast.cc

@@ -931,7 +931,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			(*it)->str = (*it)->str.substr(1);
 		if (defer)
 			(*it)->str = "$abstract" + (*it)->str;
-		if (design->modules.count((*it)->str)) {
+		if (design->modules_.count((*it)->str)) {
 			if (!ignore_redef)
 				log_error("Re-definition of module `%s' at %s:%d!\n",
 						(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@@ -939,7 +939,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 					(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
 			continue;
 		}
-		design->modules[(*it)->str] =  process_module(*it, defer);
+		design->modules_[(*it)->str] =  process_module(*it, defer);
 	}
 }
 
@@ -1036,10 +1036,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
 		modname = "$paramod" + stripped_name + para_info;
 	}
 
-	if (design->modules.count(modname) == 0) {
+	if (design->modules_.count(modname) == 0) {
 		new_ast->str = modname;
-		design->modules[modname] = process_module(new_ast, false);
+		design->modules_[modname] = process_module(new_ast, false);
-		design->modules[modname]->check();
+		design->modules_[modname]->check();
 	} else {
 		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
 	}

frontends/liberty/liberty.cc

@@ -476,7 +476,7 @@ struct LibertyFrontend : public Frontend {
 
 			std::string cell_name = RTLIL::escape_id(cell->args.at(0));
 
-			if (design->modules.count(cell_name)) {
+			if (design->modules_.count(cell_name)) {
 				if (flag_ignore_redef)
 					continue;
 				log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
@@ -564,7 +564,7 @@ struct LibertyFrontend : public Frontend {
 			}
 
 			module->fixup_ports();
-			design->modules[module->name] = module;
+			design->modules_[module->name] = module;
 			cell_count++;
 skip_cell:;
 		}

kernel/celltypes.h

@@ -171,7 +171,7 @@ struct CellTypes
 		if (cell_types.count(type) > 0)
 			return true;
 		for (auto design : designs)
-			if (design->modules.count(type) > 0)
+			if (design->modules_.count(type) > 0)
 				return true;
 		return false;
 	}
@@ -180,9 +180,9 @@ struct CellTypes
 	{
 		if (cell_types.count(type) == 0) {
 			for (auto design : designs)
-				if (design->modules.count(type) > 0) {
+				if (design->modules_.count(type) > 0) {
-					if (design->modules.at(type)->wires_.count(port))
+					if (design->modules_.at(type)->wires_.count(port))
-						return design->modules.at(type)->wires_.at(port)->port_output;
+						return design->modules_.at(type)->wires_.at(port)->port_output;
 					return false;
 				}
 			return false;
@@ -203,9 +203,9 @@ struct CellTypes
 	{
 		if (cell_types.count(type) == 0) {
 			for (auto design : designs)
-				if (design->modules.count(type) > 0) {
+				if (design->modules_.count(type) > 0) {
-					if (design->modules.at(type)->wires_.count(port))
+					if (design->modules_.at(type)->wires_.count(port))
-						return design->modules.at(type)->wires_.at(port)->port_input;
+						return design->modules_.at(type)->wires_.at(port)->port_input;
 					return false;
 				}
 			return false;

kernel/driver.cc

@@ -234,14 +234,14 @@ static char *readline_obj_generator(const char *text, int state)
 
 		if (design->selected_active_module.empty())
 		{
-			for (auto &it : design->modules)
+			for (auto &it : design->modules_)
 				if (RTLIL::unescape_id(it.first).substr(0, len) == text)
 					obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
 		}
 		else
-		if (design->modules.count(design->selected_active_module) > 0)
+		if (design->modules_.count(design->selected_active_module) > 0)
 		{
-			RTLIL::Module *module = design->modules.at(design->selected_active_module);
+			RTLIL::Module *module = design->modules_.at(design->selected_active_module);
 
 			for (auto &it : module->wires_)
 				if (RTLIL::unescape_id(it.first).substr(0, len) == text)

kernel/rtlil.cc

@@ -175,7 +175,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 
 	del_list.clear();
 	for (auto mod_name : selected_modules) {
-		if (design->modules.count(mod_name) == 0)
+		if (design->modules_.count(mod_name) == 0)
 			del_list.push_back(mod_name);
 		selected_members.erase(mod_name);
 	}
@@ -184,7 +184,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 
 	del_list.clear();
 	for (auto &it : selected_members)
-		if (design->modules.count(it.first) == 0)
+		if (design->modules_.count(it.first) == 0)
 			del_list.push_back(it.first);
 	for (auto mod_name : del_list)
 		selected_members.erase(mod_name);
@@ -192,7 +192,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 	for (auto &it : selected_members) {
 		del_list.clear();
 		for (auto memb_name : it.second)
-			if (design->modules[it.first]->count_id(memb_name) == 0)
+			if (design->modules_[it.first]->count_id(memb_name) == 0)
 				del_list.push_back(memb_name);
 		for (auto memb_name : del_list)
 			it.second.erase(memb_name);
@@ -203,8 +203,8 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 	for (auto &it : selected_members)
 		if (it.second.size() == 0)
 			del_list.push_back(it.first);
-		else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() +
+		else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
-				design->modules[it.first]->cells_.size() + design->modules[it.first]->processes.size())
+				design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
 			add_list.push_back(it.first);
 	for (auto mod_name : del_list)
 		selected_members.erase(mod_name);
@@ -213,7 +213,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 		selected_modules.insert(mod_name);
 	}
 
-	if (selected_modules.size() == design->modules.size()) {
+	if (selected_modules.size() == design->modules_.size()) {
 		full_selection = true;
 		selected_modules.clear();
 		selected_members.clear();
@@ -222,14 +222,14 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
 
 RTLIL::Design::~Design()
 {
-	for (auto it = modules.begin(); it != modules.end(); it++)
+	for (auto it = modules_.begin(); it != modules_.end(); it++)
 		delete it->second;
 }
 
 void RTLIL::Design::check()
 {
 #ifndef NDEBUG
-	for (auto &it : modules) {
+	for (auto &it : modules_) {
 		assert(it.first == it.second->name);
 		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		it.second->check();
@@ -239,7 +239,7 @@ void RTLIL::Design::check()
 
 void RTLIL::Design::optimize()
 {
-	for (auto &it : modules)
+	for (auto &it : modules_)
 		it.second->optimize();
 	for (auto &it : selection_stack)
 		it.optimize(this);

kernel/rtlil.h

@@ -340,7 +340,7 @@ struct RTLIL::Selection
 
 struct RTLIL::Design
 {
-	std::map<RTLIL::IdString, RTLIL::Module*> modules;
+	std::map<RTLIL::IdString, RTLIL::Module*> modules_;
 
 	std::vector<RTLIL::Selection> selection_stack;
 	std::map<RTLIL::IdString, RTLIL::Selection> selection_vars;

manual/CHAPTER_Prog/stubnets.cc

@@ -120,7 +120,7 @@ struct StubnetsPass : public Pass {
 
 		// call find_stub_nets() for each module that is either
 		// selected as a whole or contains selected objects.
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 			if (design->selected_module(it.first))
 				find_stub_nets(design, it.second, report_bits);
 	}

manual/PRESENTATION_Prog/my_cmd.cc

@@ -12,7 +12,7 @@ struct MyPass : public Pass {
             log("  %s\n", arg.c_str());
 
         log("Modules in current design:\n");
-        for (auto &mod : design->modules)
+        for (auto &mod : design->modules_)
             log("  %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
                     mod.second->wires_.size(), mod.second->cells_.size());
     }
@@ -40,11 +40,11 @@ struct Test1Pass : public Pass {
 
         log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
 
-        if (design->modules.count(module->name) != 0)
+        if (design->modules_.count(module->name) != 0)
             log_error("A module with the name %s already exists!\n",
                     RTLIL::id2cstr(module->name));
 
-        design->modules[module->name] = module;
+        design->modules_[module->name] = module;
     }
 } Test1Pass;
 
@@ -56,7 +56,7 @@ struct Test2Pass : public Pass {
         if (design->selection_stack.back().empty())
             log_cmd_error("This command can't operator on an empty selection!\n");
 
-        RTLIL::Module *module = design->modules.at("\\test");
+        RTLIL::Module *module = design->modules_.at("\\test");
 
         RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
                                                    y(module->wires_.at("\\y"));

passes/abc/abc.cc

@@ -684,7 +684,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 		free(p);
 
 		log_header("Re-integrating ABC results.\n");
-		RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"];
+		RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
 		if (mapped_mod == NULL)
 			log_error("ABC output file does not contain a module `netlist'.\n");
 		for (auto &it : mapped_mod->wires_) {
@@ -1000,7 +1000,7 @@ struct AbcPass : public Pass {
 		if (!constr_file.empty() && liberty_file.empty())
 			log_cmd_error("Got -constr but no -liberty!\n");
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second)) {
 				if (mod_it.second->processes.size() > 0)
 					log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());

passes/abc/blifparse.cc

@@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
 
 	int port_count = 0;
 	module->name = "\\netlist";
-	design->modules[module->name] = module;
+	design->modules_[module->name] = module;
 
 	size_t buffer_size = 4096;
 	char *buffer = (char*)malloc(buffer_size);

passes/cmds/add.cc

@@ -64,10 +64,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 
 	for (auto &it : module->cells_)
 	{
-		if (design->modules.count(it.second->type) == 0)
+		if (design->modules_.count(it.second->type) == 0)
 			continue;
 
-		RTLIL::Module *mod = design->modules.at(it.second->type);
+		RTLIL::Module *mod = design->modules_.at(it.second->type);
 		if (!design->selected_whole_module(mod->name))
 			continue;
 		if (mod->get_bool_attribute("\\blackbox"))
@@ -136,7 +136,7 @@ struct AddPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod : design->modules)
+		for (auto &mod : design->modules_)
 		{
 			RTLIL::Module *module = mod.second;
 			if (!design->selected_whole_module(module->name))

passes/cmds/connect.cc

@@ -75,7 +75,7 @@ struct ConnectPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		RTLIL::Module *module = NULL;
-		for (auto &it : design->modules) {
+		for (auto &it : design->modules_) {
 			if (!design->selected(it.second))
 				continue;
 			if (module != NULL)

passes/cmds/connwrappers.cc

@@ -197,7 +197,7 @@ struct ConnwrappersPass : public Pass {
 
 		log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				worker.work(design, mod_it.second);
 	}

passes/cmds/copy.cc

@@ -41,14 +41,14 @@ struct CopyPass : public Pass {
 		std::string src_name = RTLIL::escape_id(args[1]);
 		std::string trg_name = RTLIL::escape_id(args[2]);
 
-		if (design->modules.count(src_name) == 0)
+		if (design->modules_.count(src_name) == 0)
 			log_cmd_error("Can't find source module %s.\n", src_name.c_str());
 
-		if (design->modules.count(trg_name) != 0)
+		if (design->modules_.count(trg_name) != 0)
 			log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
 
-		design->modules[trg_name] = design->modules.at(src_name)->clone();
+		design->modules_[trg_name] = design->modules_.at(src_name)->clone();
-		design->modules[trg_name]->name = trg_name;
+		design->modules_[trg_name]->name = trg_name;
 	}
 } CopyPass;
  

passes/cmds/delete.cc

@@ -66,7 +66,7 @@ struct DeletePass : public Pass {
 
 		std::vector<std::string> delete_mods;
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
 				delete_mods.push_back(mod_it.first);
@@ -134,8 +134,8 @@ struct DeletePass : public Pass {
 		}
 
 		for (auto &it : delete_mods) {
-			delete design->modules.at(it);
+			delete design->modules_.at(it);
-			design->modules.erase(it);
+			design->modules_.erase(it);
 		}
 	}
 } DeletePass;

passes/cmds/design.cc

@@ -165,7 +165,7 @@ struct DesignPass : public Pass {
 				argidx = args.size();
 			}
 
-			for (auto &it : copy_from_design->modules) {
+			for (auto &it : copy_from_design->modules_) {
 				if (sel.selected_whole_module(it.first)) {
 					copy_src_modules.push_back(it.second);
 					continue;
@@ -192,10 +192,10 @@ struct DesignPass : public Pass {
 			{
 				std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name);
 
-				if (copy_to_design->modules.count(trg_name))
+				if (copy_to_design->modules_.count(trg_name))
-					delete copy_to_design->modules.at(trg_name);
+					delete copy_to_design->modules_.at(trg_name);
-				copy_to_design->modules[trg_name] = mod->clone();
+				copy_to_design->modules_[trg_name] = mod->clone();
-				copy_to_design->modules[trg_name]->name = trg_name;
+				copy_to_design->modules_[trg_name]->name = trg_name;
 			}
 		}
 
@@ -203,8 +203,8 @@ struct DesignPass : public Pass {
 		{
 			RTLIL::Design *design_copy = new RTLIL::Design;
 
-			for (auto &it : design->modules)
+			for (auto &it : design->modules_)
-				design_copy->modules[it.first] = it.second->clone();
+				design_copy->modules_[it.first] = it.second->clone();
 
 			design_copy->selection_stack = design->selection_stack;
 			design_copy->selection_vars = design->selection_vars;
@@ -221,9 +221,9 @@ struct DesignPass : public Pass {
 
 		if (reset_mode || !load_name.empty() || push_mode || pop_mode)
 		{
-			for (auto &it : design->modules)
+			for (auto &it : design->modules_)
 				delete it.second;
-			design->modules.clear();
+			design->modules_.clear();
 
 			design->selection_stack.clear();
 			design->selection_vars.clear();
@@ -239,8 +239,8 @@ struct DesignPass : public Pass {
 			if (pop_mode)
 				pushed_designs.pop_back();
 
-			for (auto &it : saved_design->modules)
+			for (auto &it : saved_design->modules_)
-				design->modules[it.first] = it.second->clone();
+				design->modules_[it.first] = it.second->clone();
 
 			design->selection_stack = saved_design->selection_stack;
 			design->selection_vars = saved_design->selection_vars;

passes/cmds/rename.cc

@@ -96,7 +96,7 @@ struct RenamePass : public Pass {
 		{
 			extra_args(args, argidx, design);
 
-			for (auto &mod : design->modules)
+			for (auto &mod : design->modules_)
 			{
 				int counter = 0;
 
@@ -128,7 +128,7 @@ struct RenamePass : public Pass {
 		{
 			extra_args(args, argidx, design);
 
-			for (auto &mod : design->modules)
+			for (auto &mod : design->modules_)
 			{
 				RTLIL::Module *module = mod.second;
 				if (!design->selected(module))
@@ -163,19 +163,19 @@ struct RenamePass : public Pass {
 
 			if (!design->selected_active_module.empty())
 			{
-				if (design->modules.count(design->selected_active_module) > 0)
+				if (design->modules_.count(design->selected_active_module) > 0)
-					rename_in_module(design->modules.at(design->selected_active_module), from_name, to_name);
+					rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name);
 			}
 			else
 			{
-				for (auto &mod : design->modules) {
+				for (auto &mod : design->modules_) {
 					if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
 						to_name = RTLIL::escape_id(to_name);
 						log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
 						RTLIL::Module *module = mod.second;
-						design->modules.erase(module->name);
+						design->modules_.erase(module->name);
 						module->name = to_name;
-						design->modules[module->name] = module;
+						design->modules_[module->name] = module;
 						goto rename_ok;
 					}
 				}

passes/cmds/scatter.cc

@@ -43,7 +43,7 @@ struct ScatterPass : public Pass {
 		CellTypes ct(design);
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			if (!design->selected(mod_it.second))
 				continue;

passes/cmds/scc.cc

@@ -280,7 +280,7 @@ struct SccPass : public Pass {
 
 		RTLIL::Selection newSelection(false);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 			{
 				SccWorker worker(design, mod_it.second, allCellTypes, maxDepth);

passes/cmds/select.cc

@@ -151,7 +151,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
 
 	RTLIL::Selection new_sel(false);
 
-	for (auto &mod_it : design->modules)
+	for (auto &mod_it : design->modules_)
 	{
 		if (lhs.selected_whole_module(mod_it.first))
 			continue;
@@ -181,13 +181,13 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
 
 static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
 {
-	for (auto &mod_it : design->modules)
+	for (auto &mod_it : design->modules_)
 	{
 		if (lhs.selected_whole_module(mod_it.first))
 		{
 			for (auto &cell_it : mod_it.second->cells_)
 			{
-				if (design->modules.count(cell_it.second->type) == 0)
+				if (design->modules_.count(cell_it.second->type) == 0)
 					continue;
 				lhs.selected_modules.insert(cell_it.second->type);
 			}
@@ -205,7 +205,7 @@ static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs)
 
 static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
 {
-	for (auto &mod_it : design->modules)
+	for (auto &mod_it : design->modules_)
 	{
 		if (lhs.selected_whole_module(mod_it.first))
 			continue;
@@ -260,7 +260,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
 		if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0)
 			return;
 		lhs.full_selection = false;
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 			lhs.selected_modules.insert(it.first);
 	}
 
@@ -271,10 +271,10 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
 
 	for (auto &it : rhs.selected_members)
 	{
-		if (design->modules.count(it.first) == 0)
+		if (design->modules_.count(it.first) == 0)
 			continue;
 
-		RTLIL::Module *mod = design->modules[it.first];
+		RTLIL::Module *mod = design->modules_[it.first];
 
 		if (lhs.selected_modules.count(mod->name) > 0)
 		{
@@ -304,7 +304,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co
 
 	if (lhs.full_selection) {
 		lhs.full_selection = false;
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 			lhs.selected_modules.insert(it.first);
 	}
 
@@ -368,7 +368,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 {
 	int sel_objects = 0;
 	bool is_input, is_output;
-	for (auto &mod_it : design->modules)
+	for (auto &mod_it : design->modules_)
 	{
 		if (lhs.selected_whole_module(mod_it.first) || !lhs.selected_module(mod_it.first))
 			continue;
@@ -684,7 +684,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 	}
 	
 	sel.full_selection = false;
-	for (auto &mod_it : design->modules)
+	for (auto &mod_it : design->modules_)
 	{
 		if (arg_mod.substr(0, 2) == "A:") {
 			if (!match_attr(mod_it.second->attributes, arg_mod.substr(2)))
@@ -1078,7 +1078,7 @@ struct SelectPass : public Pass {
 			}
 			if (arg == "-module" && argidx+1 < args.size()) {
 				RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
-				if (design->modules.count(mod_name) == 0)
+				if (design->modules_.count(mod_name) == 0)
 					log_cmd_error("No such module: %s\n", id2cstr(mod_name));
 				design->selected_active_module = mod_name;
 				got_module = true;
@@ -1147,7 +1147,7 @@ struct SelectPass : public Pass {
 			if (work_stack.size() > 0)
 				sel = &work_stack.back();
 			sel->optimize(design);
-			for (auto mod_it : design->modules)
+			for (auto mod_it : design->modules_)
 			{
 				if (sel->selected_whole_module(mod_it.first) && list_mode)
 					log("%s\n", id2cstr(mod_it.first));
@@ -1217,7 +1217,7 @@ struct SelectPass : public Pass {
 				log_cmd_error("No selection to check.\n");
 			RTLIL::Selection *sel = &work_stack.back();
 			sel->optimize(design);
-			for (auto mod_it : design->modules)
+			for (auto mod_it : design->modules_)
 				if (sel->selected_module(mod_it.first)) {
 					for (auto &it : mod_it.second->wires_)
 						if (sel->selected_member(mod_it.first, it.first))
@@ -1299,15 +1299,15 @@ struct CdPass : public Pass {
 
 		std::string modname = RTLIL::escape_id(args[1]);
 
-		if (design->modules.count(modname) == 0 && !design->selected_active_module.empty()) {
+		if (design->modules_.count(modname) == 0 && !design->selected_active_module.empty()) {
 			RTLIL::Module *module = NULL;
-			if (design->modules.count(design->selected_active_module) > 0)
+			if (design->modules_.count(design->selected_active_module) > 0)
-				module = design->modules.at(design->selected_active_module);
+				module = design->modules_.at(design->selected_active_module);
 			if (module != NULL && module->cells_.count(modname) > 0)
 				modname = module->cells_.at(modname)->type;
 		}
 
-		if (design->modules.count(modname) > 0) {
+		if (design->modules_.count(modname) > 0) {
 			design->selected_active_module = modname;
 			design->selection_stack.back() = RTLIL::Selection();
 			select_filter_active_mod(design, design->selection_stack.back());
@@ -1368,12 +1368,12 @@ struct LsPass : public Pass {
 
 		if (design->selected_active_module.empty())
 		{
-			counter += log_matches("modules", pattern, design->modules);
+			counter += log_matches("modules", pattern, design->modules_);
 		}
 		else
-		if (design->modules.count(design->selected_active_module) > 0)
+		if (design->modules_.count(design->selected_active_module) > 0)
 		{
-			RTLIL::Module *module = design->modules.at(design->selected_active_module);
+			RTLIL::Module *module = design->modules_.at(design->selected_active_module);
 			counter += log_matches("wires", pattern, module->wires_);
 			counter += log_matches("memories", pattern, module->memories);
 			counter += log_matches("cells", pattern, module->cells_);

passes/cmds/setattr.cc

@@ -98,7 +98,7 @@ struct SetattrPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod : design->modules)
+		for (auto &mod : design->modules_)
 		{
 			RTLIL::Module *module = mod.second;
 
@@ -164,7 +164,7 @@ struct SetparamPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod : design->modules)
+		for (auto &mod : design->modules_)
 		{
 			RTLIL::Module *module = mod.second;
 

passes/cmds/setundef.cc

@@ -115,7 +115,7 @@ struct SetundefPass : public Pass {
 		if (!got_value)
 			log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n");
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			RTLIL::Module *module = mod_it.second;
 			if (!design->selected(module))

passes/cmds/show.cc

@@ -506,7 +506,7 @@ struct ShowWorker
 
 		design->optimize();
 		page_counter = 0;
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			module = mod_it.second;
 			if (!design->selected_module(module->name))
@@ -692,7 +692,7 @@ struct ShowPass : public Pass {
 
 		if (format != "ps") {
 			int modcount = 0;
-			for (auto &mod_it : design->modules) {
+			for (auto &mod_it : design->modules_) {
 				if (mod_it.second->get_bool_attribute("\\blackbox"))
 					continue;
 				if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())

passes/cmds/splice.cc

@@ -327,7 +327,7 @@ struct SplicePass : public Pass {
 
 		log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			if (!design->selected(mod_it.second))
 				continue;

passes/cmds/splitnets.cc

@@ -117,7 +117,7 @@ struct SplitnetsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			RTLIL::Module *module = mod_it.second;
 			if (!design->selected(module))

passes/cmds/stat.cc

@@ -166,16 +166,16 @@ struct StatPass : public Pass {
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
 			if (args[argidx] == "-top" && argidx+1 < args.size()) {
-				if (design->modules.count(RTLIL::escape_id(args[argidx+1])) == 0)
+				if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0)
 					log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str());
-				top_mod = design->modules.at(RTLIL::escape_id(args[++argidx]));
+				top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx]));
 				continue;
 			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 		{
 			if (!design->selected_module(it.first))
 				continue;

passes/fsm/fsm_detect.cc

@@ -148,7 +148,7 @@ struct FsmDetectPass : public Pass {
 		ct.setup_stdcells();
 		ct.setup_stdcells_mem();
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			if (!design->selected(mod_it.second))
 				continue;

passes/fsm/fsm_expand.cc

@@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass {
 		log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			std::vector<RTLIL::Cell*> fsm_cells;

passes/fsm/fsm_export.cc

@@ -174,7 +174,7 @@ struct FsmExportPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				for (auto &cell_it : mod_it.second->cells_)
 					if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {

passes/fsm/fsm_extract.cc

@@ -330,7 +330,7 @@ struct FsmExtractPass : public Pass {
 		ct.setup_stdcells();
 		ct.setup_stdcells_mem();
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			if (!design->selected(mod_it.second))
 				continue;

passes/fsm/fsm_info.cc

@@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass {
 		log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				for (auto &cell_it : mod_it.second->cells_)
 					if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {

passes/fsm/fsm_map.cc

@@ -309,7 +309,7 @@ struct FsmMapPass : public Pass {
 		log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			std::vector<RTLIL::Cell*> fsm_cells;

passes/fsm/fsm_opt.cc

@@ -288,7 +288,7 @@ struct FsmOptPass : public Pass {
 		log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n");
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (design->selected(mod_it.second))
 				for (auto &cell_it : mod_it.second->cells_)
 					if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second))

passes/fsm/fsm_recode.cc

@@ -144,7 +144,7 @@ struct FsmRecodePass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				for (auto &cell_it : mod_it.second->cells_)
 					if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))

passes/hierarchy/hierarchy.cc

@@ -37,11 +37,11 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 {
 	std::set<std::string> found_celltypes;
 
-	for (auto i1 : design->modules)
+	for (auto i1 : design->modules_)
 	for (auto i2 : i1.second->cells_)
 	{
 		RTLIL::Cell *cell = i2.second;
-		if (cell->type[0] == '$' || design->modules.count(cell->type) > 0)
+		if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0)
 			continue;
 		for (auto &pattern : celltypes)
 			if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE))
@@ -55,7 +55,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		std::map<std::string, int> portwidths;
 		log("Generate module for cell type %s:\n", celltype.c_str());
 
-		for (auto i1 : design->modules)
+		for (auto i1 : design->modules_)
 		for (auto i2 : i1.second->cells_)
 			if (i2.second->type == celltype) {
 				for (auto &conn : i2.second->connections()) {
@@ -115,7 +115,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
 		mod->attributes["\\blackbox"] = RTLIL::Const(1);
-		design->modules[mod->name] = mod;
+		design->modules_[mod->name] = mod;
 
 		for (auto &decl : ports) {
 			RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
@@ -151,11 +151,11 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 			cell->type = cell->type.substr(pos_type + 1);
 		}
 
-		if (design->modules.count(cell->type) == 0)
+		if (design->modules_.count(cell->type) == 0)
 		{
-			if (design->modules.count("$abstract" + cell->type))
+			if (design->modules_.count("$abstract" + cell->type))
 			{
-				cell->type = design->modules.at("$abstract" + cell->type)->derive(design, cell->parameters);
+				cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters);
 				cell->parameters.clear();
 				did_something = true;
 				continue;
@@ -189,7 +189,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 			continue;
 
 		loaded_module:
-			if (design->modules.count(cell->type) == 0)
+			if (design->modules_.count(cell->type) == 0)
 				log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
 			did_something = true;
 		}
@@ -197,10 +197,10 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 		if (cell->parameters.size() == 0)
 			continue;
 
-		if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
+		if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox"))
 			continue;
 
-		RTLIL::Module *mod = design->modules[cell->type];
+		RTLIL::Module *mod = design->modules_[cell->type];
 		cell->type = mod->derive(design, cell->parameters);
 		cell->parameters.clear();
 		did_something = true;
@@ -211,10 +211,10 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 		RTLIL::Cell *cell = it.first;
 		int idx = it.second.first, num = it.second.second;
 
-		if (design->modules.count(cell->type) == 0)
+		if (design->modules_.count(cell->type) == 0)
 			log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 
-		RTLIL::Module *mod = design->modules[cell->type];
+		RTLIL::Module *mod = design->modules_[cell->type];
 
 		for (auto &conn : cell->connections_) {
 			int conn_size = conn.second.size();
@@ -253,8 +253,8 @@ static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &us
 	used.insert(mod);
 
 	for (auto &it : mod->cells_) {
-		if (design->modules.count(it.second->type) > 0)
+		if (design->modules_.count(it.second->type) > 0)
-			hierarchy_worker(design, used, design->modules[it.second->type], indent+4);
+			hierarchy_worker(design, used, design->modules_[it.second->type], indent+4);
 	}
 }
 
@@ -264,7 +264,7 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib,
 	hierarchy_worker(design, used, top, 0);
 
 	std::vector<RTLIL::Module*> del_modules;
-	for (auto &it : design->modules)
+	for (auto &it : design->modules_)
 		if (used.count(it.second) == 0)
 			del_modules.push_back(it.second);
 
@@ -274,7 +274,7 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib,
 		if (!purge_lib && mod->get_bool_attribute("\\blackbox"))
 			continue;
 		log("Removing unused module `%s'.\n", mod->name.c_str());
-		design->modules.erase(mod->name);
+		design->modules_.erase(mod->name);
 		delete mod;
 	}
 
@@ -412,11 +412,11 @@ struct HierarchyPass : public Pass {
 			if (args[argidx] == "-top") {
 				if (++argidx >= args.size())
 					log_cmd_error("Option -top requires an additional argument!\n");
-				top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL;
+				top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
-				if (top_mod == NULL && design->modules.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
+				if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
 					std::map<RTLIL::IdString, RTLIL::Const> empty_parameters;
-					design->modules.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
+					design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
-					top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL;
+					top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
 				}
 				if (top_mod == NULL)
 					log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
@@ -434,7 +434,7 @@ struct HierarchyPass : public Pass {
 		log_push();
 
 		if (top_mod == NULL)
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_mod = mod_it.second;
 
@@ -446,13 +446,13 @@ struct HierarchyPass : public Pass {
 		while (did_something) {
 			did_something = false;
 			std::vector<std::string> modnames;
-			modnames.reserve(design->modules.size());
+			modnames.reserve(design->modules_.size());
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				modnames.push_back(mod_it.first);
 			for (auto &modname : modnames) {
-				if (design->modules.count(modname) == 0)
+				if (design->modules_.count(modname) == 0)
 					continue;
-				if (expand_module(design, design->modules[modname], flag_check, libdirs))
+				if (expand_module(design, design->modules_[modname], flag_check, libdirs))
 					did_something = true;
 			}
 			if (did_something)
@@ -465,7 +465,7 @@ struct HierarchyPass : public Pass {
 		}
 
 		if (top_mod != NULL) {
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				if (mod_it.second == top_mod)
 					mod_it.second->attributes["\\top"] = RTLIL::Const(1);
 				else
@@ -478,14 +478,14 @@ struct HierarchyPass : public Pass {
 			std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
 			std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
 
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 			for (auto &cell_it : mod_it.second->cells_) {
 				RTLIL::Cell *cell = cell_it.second;
-				if (design->modules.count(cell->type) == 0)
+				if (design->modules_.count(cell->type) == 0)
 					continue;
 				for (auto &conn : cell->connections())
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
-						pos_mods.insert(design->modules.at(cell->type));
+						pos_mods.insert(design->modules_.at(cell->type));
 						pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
 						break;
 					}
@@ -507,7 +507,7 @@ struct HierarchyPass : public Pass {
 				for (auto &conn : cell->connections())
 					if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 						int id = atoi(conn.first.c_str()+1);
-						std::pair<RTLIL::Module*,int> key(design->modules.at(cell->type), id);
+						std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id);
 						if (pos_map.count(key) == 0) {
 							log("  Failed to map positional argument %d of cell %s.%s (%s).\n",
 									id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));

passes/hierarchy/submod.cc

@@ -105,7 +105,7 @@ struct SubmodWorker
 
 		RTLIL::Module *new_mod = new RTLIL::Module;
 		new_mod->name = submod.full_name;
-		design->modules[new_mod->name] = new_mod;
+		design->modules_[new_mod->name] = new_mod;
 		int port_counter = 1, auto_name_counter = 1;
 
 		std::set<std::string> all_wire_names;
@@ -229,7 +229,7 @@ struct SubmodWorker
 				if (submodules.count(submod_str) == 0) {
 					submodules[submod_str].name = submod_str;
 					submodules[submod_str].full_name = module->name + "_" + submod_str;
-					while (design->modules.count(submodules[submod_str].full_name) != 0 ||
+					while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
 							module->count_id(submodules[submod_str].full_name) != 0)
 						submodules[submod_str].full_name += "_";
 				}
@@ -312,12 +312,12 @@ struct SubmodPass : public Pass {
 			while (did_something) {
 				did_something = false;
 				std::vector<std::string> queued_modules;
-				for (auto &mod_it : design->modules)
+				for (auto &mod_it : design->modules_)
 					if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
 						queued_modules.push_back(mod_it.first);
 				for (auto &modname : queued_modules)
-					if (design->modules.count(modname) != 0) {
+					if (design->modules_.count(modname) != 0) {
-						SubmodWorker worker(design, design->modules[modname]);
+						SubmodWorker worker(design, design->modules_[modname]);
 						handled_modules.insert(modname);
 						did_something = true;
 					}
@@ -328,7 +328,7 @@ struct SubmodPass : public Pass {
 		else
 		{
 			RTLIL::Module *module = NULL;
-			for (auto &mod_it : design->modules) {
+			for (auto &mod_it : design->modules_) {
 				if (!design->selected_module(mod_it.first))
 					continue;
 				if (module != NULL)

passes/memory/memory_collect.cc

@@ -200,7 +200,7 @@ struct MemoryCollectPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
 		log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
 		extra_args(args, 1, design);
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				handle_module(design, mod_it.second);
 	}

passes/memory/memory_dff.cc

@@ -212,7 +212,7 @@ struct MemoryDffPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				handle_module(design, mod_it.second, flag_wr_only);
 	}

passes/memory/memory_map.cc

@@ -317,7 +317,7 @@ struct MemoryMapPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
 		log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
 		extra_args(args, 1, design);
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				handle_module(design, mod_it.second);
 	}

passes/memory/memory_share.cc

@@ -734,7 +734,7 @@ struct MemorySharePass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
 		log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
 		extra_args(args, 1, design);
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				MemoryShareWorker(design, mod_it.second);
 	}

passes/memory/memory_unpack.cc

@@ -102,7 +102,7 @@ struct MemoryUnpackPass : public Pass {
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
 		log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
 		extra_args(args, 1, design);
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				handle_module(design, mod_it.second);
 	}

passes/opt/opt_clean.cc

@@ -338,7 +338,7 @@ struct OptCleanPass : public Pass {
 		ct_reg.setup_internals_mem();
 		ct_reg.setup_stdcells_mem();
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected_whole_module(mod_it.first)) {
 				if (design->selected(mod_it.second))
 					log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
@@ -402,7 +402,7 @@ struct CleanPass : public Pass {
 		count_rm_cells = 0;
 		count_rm_wires = 0;
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0)
 				do {
 					OPT_DID_SOMETHING = false;

passes/opt/opt_const.cc

@@ -939,7 +939,7 @@ struct OptConstPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			if (undriven)
 				replace_undriven(design, mod_it.second);

passes/opt/opt_muxtree.cc

@@ -423,7 +423,7 @@ struct OptMuxtreePass : public Pass {
 		extra_args(args, 1, design);
 
 		int total_count = 0;
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected_whole_module(mod_it.first)) {
 				if (design->selected(mod_it.second))
 					log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));

passes/opt/opt_reduce.cc

@@ -367,7 +367,7 @@ struct OptReducePass : public Pass {
 		extra_args(args, argidx, design);
 
 		int total_count = 0;
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			OptReduceWorker worker(design, mod_it.second, do_fine);

passes/opt/opt_rmdff.cc

@@ -166,7 +166,7 @@ struct OptRmdffPass : public Pass {
 
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			if (!design->selected(mod_it.second))
 				continue;

passes/opt/opt_share.cc

@@ -315,7 +315,7 @@ struct OptSharePass : public Pass {
 		extra_args(args, argidx, design);
 
 		int total_count = 0;
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			OptShareWorker worker(design, mod_it.second, mode_nomux);

passes/proc/proc_arst.cc

@@ -236,7 +236,7 @@ struct ProcArstPass : public Pass {
 
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second)) {
 				SigMap assign_map(mod_it.second);
 				for (auto &proc_it : mod_it.second->processes) {

passes/proc/proc_clean.cc

@@ -149,7 +149,7 @@ struct ProcCleanPass : public Pass {
 
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			std::vector<std::string> delme;
 			if (!design->selected(mod_it.second))
 				continue;

passes/proc/proc_dff.cc

@@ -371,7 +371,7 @@ struct ProcDffPass : public Pass {
 
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second)) {
 				ConstEval ce(mod_it.second);
 				for (auto &proc_it : mod_it.second->processes)

passes/proc/proc_init.cc

@@ -101,7 +101,7 @@ struct ProcInitPass : public Pass {
 
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				for (auto &proc_it : mod_it.second->processes)
 					if (design->selected(mod_it.second, proc_it.second))

passes/proc/proc_mux.cc

@@ -276,7 +276,7 @@ struct ProcMuxPass : public Pass {
 
 		extra_args(args, 1, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				for (auto &proc_it : mod_it.second->processes)
 					if (design->selected(mod_it.second, proc_it.second))

passes/proc/proc_rmdead.cc

@@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass {
 		extra_args(args, 1, design);
 
 		int total_counter = 0;
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			for (auto &proc_it : mod_it.second->processes) {

passes/sat/eval.cc

@@ -306,10 +306,10 @@ struct VlogHammerReporter
 	{
 		for (auto name : split(module_list, ",")) {
 			RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
-			if (design->modules.count(esc_name) == 0)
+			if (design->modules_.count(esc_name) == 0)
 				log_error("Can't find module %s in current design!\n", name.c_str());
 			log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
-			modules.push_back(design->modules.at(esc_name));
+			modules.push_back(design->modules_.at(esc_name));
 			module_names.push_back(name);
 		}
 
@@ -416,11 +416,11 @@ struct EvalPass : public Pass {
 				/* this should only be used for regression testing of ConstEval -- see vloghammer */
 				std::string mod1_name = RTLIL::escape_id(args[++argidx]);
 				std::string mod2_name = RTLIL::escape_id(args[++argidx]);
-				if (design->modules.count(mod1_name) == 0)
+				if (design->modules_.count(mod1_name) == 0)
 					log_error("Can't find module `%s'!\n", mod1_name.c_str());
-				if (design->modules.count(mod2_name) == 0)
+				if (design->modules_.count(mod2_name) == 0)
 					log_error("Can't find module `%s'!\n", mod2_name.c_str());
-				BruteForceEquivChecker checker(design->modules.at(mod1_name), design->modules.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
+				BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
 				if (checker.errors > 0)
 					log_cmd_error("Modules are not equivialent!\n");
 				log("Verified %s = %s (using brute-force check on %d cases).\n",
@@ -442,7 +442,7 @@ struct EvalPass : public Pass {
 		extra_args(args, argidx, design);
 
 		RTLIL::Module *module = NULL;
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second)) {
 				if (module)
 					log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",

passes/sat/expose.cc

@@ -50,7 +50,7 @@ static bool consider_cell(RTLIL::Design *design, std::set<std::string> &dff_cell
 {
 	if (cell->name[0] == '$' || dff_cells.count(cell->name))
 		return false;
-	if (cell->type.at(0) == '\\' && !design->modules.count(cell->type))
+	if (cell->type.at(0) == '\\' && !design->modules_.count(cell->type))
 		return false;
 	return true;
 }
@@ -302,7 +302,7 @@ struct ExposePass : public Pass {
 			RTLIL::Module *first_module = NULL;
 			std::set<std::string> shared_dff_wires;
 
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 			{
 				if (!design->selected(mod_it.second))
 					continue;
@@ -352,7 +352,7 @@ struct ExposePass : public Pass {
 		{
 			RTLIL::Module *first_module = NULL;
 
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 			{
 				RTLIL::Module *module = mod_it.second;
 
@@ -434,7 +434,7 @@ struct ExposePass : public Pass {
 			}
 		}
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 		{
 			RTLIL::Module *module = mod_it.second;
 
@@ -583,9 +583,9 @@ struct ExposePass : public Pass {
 
 					RTLIL::Cell *cell = it.second;
 
-					if (design->modules.count(cell->type))
+					if (design->modules_.count(cell->type))
 					{
-						RTLIL::Module *mod = design->modules.at(cell->type);
+						RTLIL::Module *mod = design->modules_.at(cell->type);
 
 						for (auto &it : mod->wires_)
 						{

passes/sat/freduce.cc

@@ -817,7 +817,7 @@ struct FreducePass : public Pass {
 		extra_args(args, argidx, design);
 
 		int bitcount = 0;
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			RTLIL::Module *module = mod_it.second;
 			if (design->selected(module))
 				bitcount += FreduceWorker(design, module).run();

passes/sat/miter.cc

@@ -63,15 +63,15 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 	std::string gate_name = RTLIL::escape_id(args[argidx++]);
 	std::string miter_name = RTLIL::escape_id(args[argidx++]);
 
-	if (design->modules.count(gold_name) == 0)
+	if (design->modules_.count(gold_name) == 0)
 		log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
-	if (design->modules.count(gate_name) == 0)
+	if (design->modules_.count(gate_name) == 0)
 		log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
-	if (design->modules.count(miter_name) != 0)
+	if (design->modules_.count(miter_name) != 0)
 		log_cmd_error("There is already a module %s!\n", gate_name.c_str());
 
-	RTLIL::Module *gold_module = design->modules.at(gold_name);
+	RTLIL::Module *gold_module = design->modules_.at(gold_name);
-	RTLIL::Module *gate_module = design->modules.at(gate_name);
+	RTLIL::Module *gate_module = design->modules_.at(gate_name);
 
 	for (auto &it : gold_module->wires_) {
 		RTLIL::Wire *w1 = it.second, *w2;
@@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
 
 	RTLIL::Module *miter_module = new RTLIL::Module;
 	miter_module->name = miter_name;
-	design->modules[miter_name] = miter_module;
+	design->modules_[miter_name] = miter_module;
 
 	RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
 	RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);

passes/sat/sat.cc

@@ -1141,7 +1141,7 @@ struct SatPass : public Pass {
 		extra_args(args, argidx, design);
 
 		RTLIL::Module *module = NULL;
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second)) {
 				if (module)
 					log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n",

passes/sat/share.cc

@@ -961,7 +961,7 @@ struct SharePass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &mod_it : design->modules)
+		for (auto &mod_it : design->modules_)
 			if (design->selected(mod_it.second))
 				ShareWorker(config, design, mod_it.second);
 	}

passes/techmap/dfflibmap.cc

@@ -524,7 +524,7 @@ struct DfflibmapPass : public Pass {
  		log("  final dff cell mappings:\n");
  		logmap_all();
 
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 			if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
 				dfflibmap(design, it.second);
 

passes/techmap/extract.cc

@@ -604,9 +604,9 @@ struct ExtractPass : public Pass {
 						delete map;
 						log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
 					}
-					for (auto &it : saved_designs.at(filename.substr(1))->modules)
+					for (auto &it : saved_designs.at(filename.substr(1))->modules_)
-						if (!map->modules.count(it.first))
+						if (!map->modules_.count(it.first))
-							map->modules[it.first] = it.second->clone();
+							map->modules_[it.first] = it.second->clone();
 				}
 				else
 				{
@@ -632,7 +632,7 @@ struct ExtractPass : public Pass {
 		log_header("Creating graphs for SubCircuit library.\n");
 
 		if (!mine_mode)
-			for (auto &mod_it : map->modules) {
+			for (auto &mod_it : map->modules_) {
 				SubCircuit::Graph mod_graph;
 				std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first);
 				log("Creating needle graph %s.\n", graph_name.c_str());
@@ -643,7 +643,7 @@ struct ExtractPass : public Pass {
 				}
 			}
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			SubCircuit::Graph mod_graph;
 			std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first);
 			log("Creating haystack graph %s.\n", graph_name.c_str());
@@ -725,7 +725,7 @@ struct ExtractPass : public Pass {
 
 				RTLIL::Module *newMod = new RTLIL::Module;
 				newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
-				map->modules[newMod->name] = newMod;
+				map->modules_[newMod->name] = newMod;
 
 				int portCounter = 1;
 				for (auto wire : wires) {

passes/techmap/hilomap.cc

@@ -104,7 +104,7 @@ struct HilomapPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 		{
 			module = it.second;
 

passes/techmap/iopadmap.cc

@@ -111,7 +111,7 @@ struct IopadmapPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 		{
 			RTLIL::Module *module = it.second;
 

passes/techmap/simplemap.cc

@@ -435,7 +435,7 @@ struct SimplemapPass : public Pass {
 		std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
 		simplemap_get_mappers(mappers);
 
-		for (auto &mod_it : design->modules) {
+		for (auto &mod_it : design->modules_) {
 			if (!design->selected(mod_it.second))
 				continue;
 			std::vector<RTLIL::Cell*> delete_cells;

passes/techmap/techmap.cc

@@ -243,7 +243,7 @@ struct TechmapWorker
 			for (auto &tpl_name : celltypeMap.at(cell->type))
 			{
 				std::string derived_name = tpl_name;
-				RTLIL::Module *tpl = map->modules[tpl_name];
+				RTLIL::Module *tpl = map->modules_[tpl_name];
 				std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
 
 				if (tpl->get_bool_attribute("\\blackbox"))
@@ -334,7 +334,7 @@ struct TechmapWorker
 				} else {
 					if (cell->parameters.size() != 0) {
 						derived_name = tpl->derive(map, parameters);
-						tpl = map->modules[derived_name];
+						tpl = map->modules_[derived_name];
 						log_continue = true;
 					}
 					techmap_cache[key] = tpl;
@@ -592,15 +592,15 @@ struct TechmapPass : public Pass {
 			}
 
 		std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
-		for (auto &it : map->modules) {
+		for (auto &it : map->modules_) {
 			if (it.first.substr(0, 2) == "\\$")
 				it.second->name = it.first.substr(1);
 			modules_new[it.second->name] = it.second;
 		}
-		map->modules.swap(modules_new);
+		map->modules_.swap(modules_new);
 
 		std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
-		for (auto &it : map->modules) {
+		for (auto &it : map->modules_) {
 			if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
 				char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
 				for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
@@ -614,7 +614,7 @@ struct TechmapPass : public Pass {
 		std::set<RTLIL::Cell*> handled_cells;
 		while (did_something) {
 			did_something = false;
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
 					did_something = true;
 			if (did_something)
@@ -653,12 +653,12 @@ struct FlattenPass : public Pass {
 		TechmapWorker worker;
 
 		std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
-		for (auto &it : design->modules)
+		for (auto &it : design->modules_)
 			celltypeMap[it.first].insert(it.first);
 
 		RTLIL::Module *top_mod = NULL;
 		if (design->full_selection())
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
 					top_mod = mod_it.second;
 
@@ -670,7 +670,7 @@ struct FlattenPass : public Pass {
 				if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
 					did_something = true;
 			} else {
-				for (auto &mod_it : design->modules)
+				for (auto &mod_it : design->modules_)
 					if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
 						did_something = true;
 			}
@@ -680,14 +680,14 @@ struct FlattenPass : public Pass {
 
 		if (top_mod != NULL) {
 			std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
-			for (auto &mod_it : design->modules)
+			for (auto &mod_it : design->modules_)
 				if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) {
 					new_modules[mod_it.first] = mod_it.second;
 				} else {
 					log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
 					delete mod_it.second;
 				}
-			design->modules.swap(new_modules);
+			design->modules_.swap(new_modules);
 		}
 
 		log_pop();