mirror of https://github.com/YosysHQ/yosys.git
Fixed temp net name generation in rtlil process generator for abbreviated name matching
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c60aaf8fa3
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@ -361,6 +361,8 @@ struct AST_INTERNAL::ProcessGenerator
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do {
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do {
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wire->name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
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wire->name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
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chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
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chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
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if (chunk.wire->name.find('$') != std::string::npos)
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wire->name += stringf("$%d", RTLIL::autoidx++);
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} while (current_module->wires.count(wire->name) > 0);
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} while (current_module->wires.count(wire->name) > 0);
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wire->width = chunk.width;
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wire->width = chunk.width;
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current_module->wires[wire->name] = wire;
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current_module->wires[wire->name] = wire;
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