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For case select values use Sa instead of Sx and Sz

This commit is contained in:
Miodrag Milanovic 2023-02-08 09:22:48 +01:00
parent e7e37df91b
commit 109b88c379
2 changed files with 42 additions and 5 deletions
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40
frontends/verific/verific.cc
View File

@ -361,14 +361,50 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn
for (unsigned i = 0; i < portbus->Size(); i++) {
Net *net = inst->GetNet(portbus->ElementAtIndex(i));
if (net) {
if (net->IsConstant()) {
if (net->IsGnd())
sig.append(RTLIL::State::S0);
else if (net->IsPwr())
sig.append(RTLIL::State::S1);
else if (net->IsX())
sig.append(RTLIL::State::Sx);
else
sig.append(RTLIL::State::Sz);
}
else
sig.append(net_map_at(net));
} else
sig.append(RTLIL::State::Sz);
}
return sig;
} else {
Port *port = inst->View()->GetPort(portname);
log_assert(port != NULL);
Net *net = inst->GetNet(port);
return net_map_at(net);
}
}
RTLIL::SigSpec VerificImporter::operatorInportCase(Instance *inst, const char *portname)
{
PortBus *portbus = inst->View()->GetPortBus(portname);
if (portbus) {
RTLIL::SigSpec sig;
for (unsigned i = 0; i < portbus->Size(); i++) {
Net *net = inst->GetNet(portbus->ElementAtIndex(i));
if (net) {
if (net->IsConstant()) {
if (net->IsGnd())
sig.append(RTLIL::State::S0);
else if (net->IsPwr())
sig.append(RTLIL::State::S1);
else
sig.append(RTLIL::State::Sa);
}
else
sig.append(net_map_at(net));
} else
sig.append(RTLIL::State::Sz);
sig.append(RTLIL::State::Sa);
}
return sig;
} else {
@ -993,7 +1029,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
{
RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value");
RTLIL::SigSpec sig_select = operatorInport(inst, "select");
RTLIL::SigSpec sig_select_values = operatorInport(inst, "select_values");
RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values");
RTLIL::SigSpec sig_data_values = operatorInport(inst, "data_values");
RTLIL::SigSpec sig_data_default = operatorInport(inst, "default_value");

1
frontends/verific/verific.h
View File

@ -87,6 +87,7 @@ struct VerificImporter
RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname);
RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr);
bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name);