Allow combination of rand and const modifiers

frontends/verilog/verilog_parser.y

@@ -651,8 +651,16 @@ wire_type_signedness:
 	%empty;
 
 wire_type_const_rand:
-	TOK_CONST { current_wire_const = true; } |
-	TOK_RAND  { current_wire_rand = true;  } |
+	TOK_RAND TOK_CONST {
+	    current_wire_rand = true;
+	    current_wire_const = true;
+	} |
+	TOK_CONST {
+	    current_wire_const = true;
+	} |
+	TOK_RAND {
+	    current_wire_rand = true;
+	} |
 	%empty;
 
 opt_wire_type_token:

tests/various/rand_const.sv

@@ -0,0 +1,8 @@
+module top;
+	rand const reg rx;
+	const reg ry;
+	rand reg rz;
+	rand const integer ix;
+	const integer iy;
+	rand integer iz;
+endmodule

tests/various/rand_const.ys

@@ -0,0 +1 @@
+read_verilog -sv rand_const.sv