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Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 

synth_xilinx: add -dsp-multonly
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David Shah 2020-02-02 14:53:32 +00:00 committed by GitHub
parent b44d0e041f 65716c9982
commit 1055b6b1dd
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 7 additions and 0 deletions
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7
passes/pmgen/xilinx_dsp.cc
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@ -767,6 +767,9 @@ struct XilinxDspPass : public Pass {
log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n"); log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n");
log("device.\n"); log("device.\n");
log("\n"); log("\n");
log("This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set\n");
log("to 1.\n");
log("\n");
log("\n"); log("\n");
log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n"); log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");
log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n"); log("'(* use_dsp=\"simd\" *)' attribute attached to the output wire or attached to\n");
@ -805,6 +808,10 @@ struct XilinxDspPass : public Pass {
family = "xcu"; family = "xcu";
for (auto module : design->selected_modules()) { for (auto module : design->selected_modules()) {
if (design->scratchpad_get_bool("xilinx_dsp.multonly"))
continue;
// Experimental feature: pack $add/$sub cells with // Experimental feature: pack $add/$sub cells with
// (* use_dsp48="simd" *) into DSP48E1's using its // (* use_dsp48="simd" *) into DSP48E1's using its
// SIMD feature // SIMD feature