mirror of https://github.com/YosysHQ/yosys.git
More deadname stuff
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
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@ -154,7 +154,7 @@ always @*
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o <= i[4*W+:W];
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o <= i[4*W+:W];
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endmodule
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endmodule
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module cliffordwolf_nonexclusive_select (
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module clairexen_nonexclusive_select (
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input wire x, y, z,
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input wire x, y, z,
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input wire a, b, c, d,
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input wire a, b, c, d,
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output reg o
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output reg o
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@ -167,7 +167,7 @@ module cliffordwolf_nonexclusive_select (
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end
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end
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endmodule
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endmodule
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module cliffordwolf_freduce (
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module clairexen_freduce (
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input wire [1:0] s,
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input wire [1:0] s,
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input wire a, b, c, d,
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input wire a, b, c, d,
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output reg [3:0] o
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output reg [3:0] o
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@ -167,7 +167,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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design -load read
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hierarchy -top cliffordwolf_nonexclusive_select
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hierarchy -top clairexen_nonexclusive_select
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prep
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prep
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design -save gold
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design -save gold
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muxpack
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muxpack
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@ -182,7 +182,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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sat -verify -prove-asserts -show-ports miter
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#design -load read
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#design -load read
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#hierarchy -top cliffordwolf_freduce
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#hierarchy -top clairexen_freduce
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#prep
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#prep
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#design -save gold
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#design -save gold
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#proc; opt; freduce; opt
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#proc; opt; freduce; opt
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