diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v
index 33ece1f16..752f9ba48 100644
--- a/tests/various/muxpack.v
+++ b/tests/various/muxpack.v
@@ -154,7 +154,7 @@ always @*
      o <= i[4*W+:W];
 endmodule
 
-module cliffordwolf_nonexclusive_select (
+module clairexen_nonexclusive_select (
         input wire x, y, z,
         input wire a, b, c, d,
         output reg o
@@ -167,7 +167,7 @@ module cliffordwolf_nonexclusive_select (
         end
 endmodule
 
-module cliffordwolf_freduce (
+module clairexen_freduce (
         input wire [1:0] s,
         input wire a, b, c, d,
         output reg [3:0] o
diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys
index 3e90419af..d73fc44b4 100644
--- a/tests/various/muxpack.ys
+++ b/tests/various/muxpack.ys
@@ -167,7 +167,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 design -load read
-hierarchy -top cliffordwolf_nonexclusive_select
+hierarchy -top clairexen_nonexclusive_select
 prep
 design -save gold
 muxpack
@@ -182,7 +182,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 #design -load read
-#hierarchy -top cliffordwolf_freduce
+#hierarchy -top clairexen_freduce
 #prep
 #design -save gold
 #proc; opt; freduce; opt