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Clifford Wolf 2014-02-02 13:30:49 +01:00
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manual/PRESENTATION_ExSyn.tex
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@ -203,14 +203,6 @@ TBD
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Low-Level Synthesis}
\begin{frame}{\subsecname}
TBD
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{The ``techmap'' command} \subsection{The ``techmap'' command}
\begin{frame}{\subsecname} \begin{frame}{\subsecname}

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manual/presentation.tex
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\titlepage \titlepage
\end{frame} \end{frame}
\setcounter{section}{-1} \setcounter{section}{-2}
\section{Outline}
\section{Abstract}
\begin{frame}{Abstract}
Yosys is the first full-featured open source software for Verilog HDL
synthesis. It supports most of Verilog-2005 and is well tested with
real-world designs from the ASIC and FPGA world.
\bigskip
Learn how to use Yosys to create your own custom synthesis flows and discover
why open source HDL synthesis is important for researchers, hobbyists,
educators and engineers alike.
\bigskip
This presentation covers basic concepts of Yosys, creating simple synthesis
scripts, creating synthesis scripts for advanced applications, creating Yosys
scripts for non-synthesis applications (such as formal equivialence checking)
and writing extensions to Yosys using the C++ API.
\end{frame}
\section{Outline}
\begin{frame}{Outline} \begin{frame}{Outline}
Yosys is an Open Source Verilog synthesis tool, and more. Yosys is an Open Source Verilog synthesis tool, and more.