riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Round not floor

This commit is contained in:
Eddie Hung 2019-08-28 18:57:34 -07:00
parent 927f1e3754
commit 0f4e9f6bc5
1 changed files with 21 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
techlibs/ice40/cells_sim.v
View File

@ -180,7 +180,7 @@ endmodule
module SB_DFF ( module SB_DFF (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, D input C, D
); );
@ -190,7 +190,7 @@ endmodule
module SB_DFFE ( module SB_DFFE (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, D input C, E, D
); );
@ -201,7 +201,7 @@ endmodule
module SB_DFFSR ( module SB_DFFSR (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, R, D input C, R, D
); );
@ -214,7 +214,7 @@ endmodule
module SB_DFFR ( module SB_DFFR (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, R, D input C, R, D
); );
@ -227,7 +227,7 @@ endmodule
module SB_DFFSS ( module SB_DFFSS (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, S, D input C, S, D
); );
@ -240,7 +240,7 @@ endmodule
module SB_DFFS ( module SB_DFFS (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, S, D input C, S, D
); );
@ -253,7 +253,7 @@ endmodule
module SB_DFFESR ( module SB_DFFESR (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, R, D input C, E, R, D
); );
@ -268,7 +268,7 @@ endmodule
module SB_DFFER ( module SB_DFFER (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, R, D input C, E, R, D
); );
@ -281,7 +281,7 @@ endmodule
module SB_DFFESS ( module SB_DFFESS (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, S, D input C, E, S, D
); );
@ -296,7 +296,7 @@ endmodule
module SB_DFFES ( module SB_DFFES (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, S, D input C, E, S, D
); );
@ -311,7 +311,7 @@ endmodule
module SB_DFFN ( module SB_DFFN (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, D input C, D
); );
@ -321,7 +321,7 @@ endmodule
module SB_DFFNE ( module SB_DFFNE (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, D input C, E, D
); );
@ -332,7 +332,7 @@ endmodule
module SB_DFFNSR ( module SB_DFFNSR (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, R, D input C, R, D
); );
@ -345,7 +345,7 @@ endmodule
module SB_DFFNR ( module SB_DFFNR (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, R, D input C, R, D
); );
@ -358,7 +358,7 @@ endmodule
module SB_DFFNSS ( module SB_DFFNSS (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, S, D input C, S, D
); );
@ -371,7 +371,7 @@ endmodule
module SB_DFFNS ( module SB_DFFNS (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, S, D input C, S, D
); );
@ -384,7 +384,7 @@ endmodule
module SB_DFFNESR ( module SB_DFFNESR (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, R, D input C, E, R, D
); );
@ -399,7 +399,7 @@ endmodule
module SB_DFFNER ( module SB_DFFNER (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, R, D input C, E, R, D
); );
@ -412,7 +412,7 @@ endmodule
module SB_DFFNESS ( module SB_DFFNESS (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, S, D input C, E, S, D
); );
@ -427,7 +427,7 @@ endmodule
module SB_DFFNES ( module SB_DFFNES (
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output `SB_DFF_REG, output `SB_DFF_REG,
input C, E, S, D input C, E, S, D
); );
@ -817,7 +817,7 @@ module ICESTORM_LC (
input I0, I1, I2, I3, CIN, CLK, CEN, SR, input I0, I1, I2, I3, CIN, CLK, CEN, SR,
output LO, output LO,
`ABC_ARRIVAL_HX(540) `ABC_ARRIVAL_HX(540)
`ABC_ARRIVAL_LP(795) `ABC_ARRIVAL_LP(796)
output O, output O,
output COUT output COUT
); );