From 0ecc2e597fe149a94fdf56949ad1c2721e16fc79 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 12 Mar 2024 15:23:42 +0100
Subject: [PATCH] PLLs

---
 techlibs/nanoxplore/cells_bb.v     | 168 -----------------------------
 techlibs/nanoxplore/cells_bb_l.v   |  32 ++++++
 techlibs/nanoxplore/cells_bb_m.v   |  23 ++++
 techlibs/nanoxplore/cells_bb_u.v   |  64 +++++++++++
 techlibs/nanoxplore/cells_wrap_u.v | 112 ++++++++++++++++++-
 5 files changed, 230 insertions(+), 169 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index f01d7571f..7b49616ce 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -5846,174 +5846,6 @@ endmodule
 //    parameter lut_table = 16'b0000000000000000;
 //endmodule
 
-(* blackbox *)
-module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
-    output D1;
-    output D2;
-    output D3;
-    input FBK;
-    output OSC;
-    output RDY;
-    input REF;
-    output VCO;
-    parameter clk_outdiv1 = 0;
-    parameter clk_outdiv2 = 0;
-    parameter clk_outdiv3 = 0;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 0;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_div_on = 1'b0;
-    parameter fbk_intdiv = 2;
-    parameter location = "";
-    parameter ref_div_on = 1'b0;
-    parameter vco_range = 0;
-endmodule
-
-(* blackbox *)
-module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
-    output CAL_LOCKED;
-    output DIVO1;
-    output DIVO2;
-    output DIVP1;
-    output DIVP2;
-    output DIVP3;
-    input FBK;
-    output LDFO;
-    output OSC;
-    output PLL_LOCKED;
-    input R;
-    input REF;
-    output REFO;
-    output VCO;
-    parameter cfg_use_pll = 1'b1;
-    parameter clk_outdivo1 = 0;
-    parameter clk_outdivp1 = 0;
-    parameter clk_outdivp2 = 0;
-    parameter clk_outdivp3o2 = 0;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 0;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_intdiv = 2;
-    parameter location = "";
-    parameter pll_cpump = 3'b010;
-    parameter ref_intdiv = 0;
-    parameter ref_osc_on = 1'b0;
-    parameter wfg_sync_cal_lock = 1'b0;
-    parameter wfg_sync_pll_lock = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
-, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
-    input ARST_CAL;
-    output CAL1;
-    output CAL2;
-    output CAL3;
-    output CAL4;
-    output CAL5;
-    output CAL_LOCKED;
-    input CLK_CAL;
-    output CLK_CAL_DIV;
-    output CLK_DIV1;
-    output CLK_DIV2;
-    output CLK_DIV3;
-    output CLK_DIV4;
-    output CLK_DIVD1;
-    output CLK_DIVD2;
-    output CLK_DIVD3;
-    output CLK_DIVD4;
-    output CLK_DIVD5;
-    input EXT_CAL1;
-    input EXT_CAL2;
-    input EXT_CAL3;
-    input EXT_CAL4;
-    input EXT_CAL5;
-    input EXT_CAL_LOCKED;
-    input FBK;
-    output LDFO;
-    output OSC;
-    output PLL_LOCKED;
-    output PLL_LOCKEDA;
-    input R;
-    input REF;
-    output REFO;
-    output VCO;
-    parameter cal_delay = 6'b011011;
-    parameter cal_div = 4'b0111;
-    parameter clk_cal_sel = 2'b01;
-    parameter clk_outdiv1 = 3'b000;
-    parameter clk_outdiv2 = 3'b000;
-    parameter clk_outdiv3 = 3'b000;
-    parameter clk_outdiv4 = 3'b000;
-    parameter clk_outdivd1 = 4'b0000;
-    parameter clk_outdivd2 = 4'b0000;
-    parameter clk_outdivd3 = 4'b0000;
-    parameter clk_outdivd4 = 4'b0000;
-    parameter clk_outdivd5 = 4'b0000;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 6'b000000;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_intdiv = 7'b0000000;
-    parameter location = "";
-    parameter pll_cpump = 4'b0000;
-    parameter pll_lock = 4'b0000;
-    parameter pll_lpf_cap = 4'b0000;
-    parameter pll_lpf_res = 4'b0000;
-    parameter pll_odf = 2'b00;
-    parameter ref_intdiv = 5'b00000;
-    parameter ref_osc_on = 1'b0;
-    parameter use_cal = 1'b0;
-    parameter use_pll = 1'b1;
-endmodule
-
-(* blackbox *)
-module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);
-    input ARST_CAL;
-    output [4:0] CAL;
-    output CAL_LOCKED;
-    input CLK_CAL;
-    output CLK_CAL_DIV;
-    output [3:0] CLK_DIV;
-    output [4:0] CLK_DIVD;
-    input [4:0] EXT_CAL;
-    input EXT_CAL_LOCKED;
-    input FBK;
-    output LDFO;
-    output OSC;
-    output PLL_LOCKED;
-    output PLL_LOCKEDA;
-    input R;
-    input REF;
-    output REFO;
-    output VCO;
-    parameter cal_delay = 6'b011011;
-    parameter cal_div = 4'b0111;
-    parameter clk_cal_sel = 2'b01;
-    parameter clk_outdiv1 = 3'b000;
-    parameter clk_outdiv2 = 3'b000;
-    parameter clk_outdiv3 = 3'b000;
-    parameter clk_outdiv4 = 3'b000;
-    parameter clk_outdivd1 = 4'b0000;
-    parameter clk_outdivd2 = 4'b0000;
-    parameter clk_outdivd3 = 4'b0000;
-    parameter clk_outdivd4 = 4'b0000;
-    parameter clk_outdivd5 = 4'b0000;
-    parameter ext_fbk_on = 1'b0;
-    parameter fbk_delay = 6'b000000;
-    parameter fbk_delay_on = 1'b0;
-    parameter fbk_intdiv = 7'b0000000;
-    parameter location = "";
-    parameter pll_cpump = 4'b0000;
-    parameter pll_lock = 4'b0000;
-    parameter pll_lpf_cap = 4'b0000;
-    parameter pll_lpf_res = 4'b0000;
-    parameter pll_odf = 2'b00;
-    parameter ref_intdiv = 5'b00000;
-    parameter ref_osc_on = 1'b0;
-    parameter use_cal = 1'b0;
-    parameter use_pll = 1'b1;
-endmodule
-
 (* blackbox *)
 module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2
 , MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
index a3a11a06c..991600e65 100644
--- a/techlibs/nanoxplore/cells_bb_l.v
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -469,3 +469,35 @@ module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15
     parameter std_mode = "";
 endmodule
 
+(* blackbox *)
+module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
+    output CAL_LOCKED;
+    output DIVO1;
+    output DIVO2;
+    output DIVP1;
+    output DIVP2;
+    output DIVP3;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cfg_use_pll = 1'b1;
+    parameter clk_outdivo1 = 0;
+    parameter clk_outdivp1 = 0;
+    parameter clk_outdivp2 = 0;
+    parameter clk_outdivp3o2 = 0;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 0;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 2;
+    parameter location = "";
+    parameter pll_cpump = 3'b010;
+    parameter ref_intdiv = 0;
+    parameter ref_osc_on = 1'b0;
+    parameter wfg_sync_cal_lock = 1'b0;
+    parameter wfg_sync_pll_lock = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
index e54c1fd8a..0be57e720 100644
--- a/techlibs/nanoxplore/cells_bb_m.v
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -378,3 +378,26 @@ module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15,
     parameter std_mode = "";
 endmodule
 
+(* blackbox *)
+module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
+    output D1;
+    output D2;
+    output D3;
+    input FBK;
+    output OSC;
+    output RDY;
+    input REF;
+    output VCO;
+    parameter clk_outdiv1 = 0;
+    parameter clk_outdiv2 = 0;
+    parameter clk_outdiv3 = 0;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 0;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_div_on = 1'b0;
+    parameter fbk_intdiv = 2;
+    parameter location = "";
+    parameter ref_div_on = 1'b0;
+    parameter vco_range = 0;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index 657cd6667..988ddb4c5 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -485,3 +485,67 @@ module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15
     parameter raw_config3 = 3'b000;
     parameter std_mode = "";
 endmodule
+
+(* blackbox *)
+module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
+, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
+    input ARST_CAL;
+    output CAL1;
+    output CAL2;
+    output CAL3;
+    output CAL4;
+    output CAL5;
+    output CAL_LOCKED;
+    input CLK_CAL;
+    output CLK_CAL_DIV;
+    output CLK_DIV1;
+    output CLK_DIV2;
+    output CLK_DIV3;
+    output CLK_DIV4;
+    output CLK_DIVD1;
+    output CLK_DIVD2;
+    output CLK_DIVD3;
+    output CLK_DIVD4;
+    output CLK_DIVD5;
+    input EXT_CAL1;
+    input EXT_CAL2;
+    input EXT_CAL3;
+    input EXT_CAL4;
+    input EXT_CAL5;
+    input EXT_CAL_LOCKED;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    output PLL_LOCKEDA;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cal_delay = 6'b011011;
+    parameter cal_div = 4'b0111;
+    parameter clk_cal_sel = 2'b01;
+    parameter clk_outdiv1 = 3'b000;
+    parameter clk_outdiv2 = 3'b000;
+    parameter clk_outdiv3 = 3'b000;
+    parameter clk_outdiv4 = 3'b000;
+    parameter clk_outdivd1 = 4'b0000;
+    parameter clk_outdivd2 = 4'b0000;
+    parameter clk_outdivd3 = 4'b0000;
+    parameter clk_outdivd4 = 4'b0000;
+    parameter clk_outdivd5 = 4'b0000;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 6'b000000;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 7'b0000000;
+    parameter location = "";
+    parameter pll_cpump = 4'b0000;
+    parameter pll_lock = 4'b0000;
+    parameter pll_lpf_cap = 4'b0000;
+    parameter pll_lpf_res = 4'b0000;
+    parameter pll_odf = 2'b00;
+    parameter ref_intdiv = 5'b00000;
+    parameter ref_osc_on = 1'b0;
+    parameter use_cal = 1'b0;
+    parameter use_pll = 1'b1;
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index 7f7fda789..be5561c3e 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -1348,4 +1348,114 @@ module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C,
     .Z55(Z[54]),
     .Z56(Z[55])
   );
-endmodule
\ No newline at end of file
+endmodule
+
+module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);
+    input ARST_CAL;
+    output [4:0] CAL;
+    output CAL_LOCKED;
+    input CLK_CAL;
+    output CLK_CAL_DIV;
+    output [3:0] CLK_DIV;
+    output [4:0] CLK_DIVD;
+    input [4:0] EXT_CAL;
+    input EXT_CAL_LOCKED;
+    input FBK;
+    output LDFO;
+    output OSC;
+    output PLL_LOCKED;
+    output PLL_LOCKEDA;
+    input R;
+    input REF;
+    output REFO;
+    output VCO;
+    parameter cal_delay = 6'b011011;
+    parameter cal_div = 4'b0111;
+    parameter clk_cal_sel = 2'b01;
+    parameter clk_outdiv1 = 3'b000;
+    parameter clk_outdiv2 = 3'b000;
+    parameter clk_outdiv3 = 3'b000;
+    parameter clk_outdiv4 = 3'b000;
+    parameter clk_outdivd1 = 4'b0000;
+    parameter clk_outdivd2 = 4'b0000;
+    parameter clk_outdivd3 = 4'b0000;
+    parameter clk_outdivd4 = 4'b0000;
+    parameter clk_outdivd5 = 4'b0000;
+    parameter ext_fbk_on = 1'b0;
+    parameter fbk_delay = 6'b000000;
+    parameter fbk_delay_on = 1'b0;
+    parameter fbk_intdiv = 7'b0000000;
+    parameter location = "";
+    parameter pll_cpump = 4'b0000;
+    parameter pll_lock = 4'b0000;
+    parameter pll_lpf_cap = 4'b0000;
+    parameter pll_lpf_res = 4'b0000;
+    parameter pll_odf = 2'b00;
+    parameter ref_intdiv = 5'b00000;
+    parameter ref_osc_on = 1'b0;
+    parameter use_cal = 1'b0;
+    parameter use_pll = 1'b1;
+
+  NX_PLL_U #(
+    .cal_delay(cal_delay),
+    .cal_div(cal_div),
+    .clk_cal_sel(clk_cal_sel),
+    .clk_outdiv1(clk_outdiv1),
+    .clk_outdiv2(clk_outdiv2),
+    .clk_outdiv3(clk_outdiv3),
+    .clk_outdiv4(clk_outdiv4),
+    .clk_outdivd1(clk_outdivd1),
+    .clk_outdivd2(clk_outdivd2),
+    .clk_outdivd3(clk_outdivd3),
+    .clk_outdivd4(clk_outdivd4),
+    .clk_outdivd5(clk_outdivd5),
+    .ext_fbk_on(ext_fbk_on),
+    .fbk_delay(fbk_delay),
+    .fbk_delay_on(fbk_delay_on),
+    .fbk_intdiv(fbk_intdiv),
+    .location(location),
+    .pll_cpump(pll_cpump),
+    .pll_lock(pll_lock),
+    .pll_lpf_cap(pll_lpf_cap),
+    .pll_lpf_res(pll_lpf_res),
+    .pll_odf(pll_odf),
+    .ref_intdiv(ref_intdiv),
+    .ref_osc_on(ref_osc_on),
+    .use_cal(use_cal),
+    .use_pll(use_pll)
+  ) _TECHMAP_REPLACE_ (
+    .ARST_CAL(ARST_CAL),
+    .CAL1(CAL[0]),
+    .CAL2(CAL[1]),
+    .CAL3(CAL[2]),
+    .CAL4(CAL[3]),
+    .CAL5(CAL[4]),
+    .CAL_LOCKED(CAL_LOCKED),
+    .CLK_CAL(CLK_CAL),
+    .CLK_CAL_DIV(CLK_CAL_DIV),
+    .CLK_DIV1(CLK_DIV[0]),
+    .CLK_DIV2(CLK_DIV[1]),
+    .CLK_DIV3(CLK_DIV[2]),
+    .CLK_DIV4(CLK_DIV[3]),
+    .CLK_DIVD1(CLK_DIVD[0]),
+    .CLK_DIVD2(CLK_DIVD[1]),
+    .CLK_DIVD3(CLK_DIVD[2]),
+    .CLK_DIVD4(CLK_DIVD[3]),
+    .CLK_DIVD5(CLK_DIVD[4]),
+    .EXT_CAL1(EXT_CAL[0]),
+    .EXT_CAL2(EXT_CAL[1]),
+    .EXT_CAL3(EXT_CAL[2]),
+    .EXT_CAL4(EXT_CAL[3]),
+    .EXT_CAL5(EXT_CAL[4]),
+    .EXT_CAL_LOCKED(EXT_CAL_LOCKED),
+    .FBK(FBK),
+    .LDFO(LDFO),
+    .OSC(OSC),
+    .PLL_LOCKED(PLL_LOCKED),
+    .PLL_LOCKEDA(PLL_LOCKEDA),
+    .R(R),
+    .REF(REF),
+    .REFO(REFO),
+    .VCO(VCO)
+  );
+endmodule