mirror of https://github.com/YosysHQ/yosys.git
Added BLIF backend
This commit is contained in:
Clifford Wolf
parent
28069e8a10
commit
0ec5542ab4
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OBJS += backends/blif/blif.o
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] Berkeley Logic Interchange Format (BLIF)
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// University of California. Berkeley. July 28, 1992
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// http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string>
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#include <assert.h>
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struct BlifDumper
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{
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FILE *f;
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RTLIL::Module *module;
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RTLIL::Design *design;
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CellTypes ct;
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BlifDumper(FILE *f, RTLIL::Module *module, RTLIL::Design *design) : f(f), module(module), design(design), ct(design)
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{
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}
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std::vector<std::string> cstr_buf;
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const char *cstr(RTLIL::IdString id)
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{
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std::string str = RTLIL::unescape_id(id);
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for (size_t i = 0; i < str.size(); i++)
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if (str[i] == '#' || str[i] == '=')
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str[i] = '?';
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cstr_buf.push_back(str);
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return cstr_buf.back().c_str();
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}
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const char *cstr(RTLIL::SigSpec sig)
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{
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sig.optimize();
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log_assert(sig.width == 1);
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if (sig.chunks.at(0).wire == NULL)
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return sig.chunks.at(0).data.bits.at(0) == RTLIL::State::S1 ? "$true" : "$false";
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std::string str = RTLIL::unescape_id(sig.chunks.at(0).wire->name);
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for (size_t i = 0; i < str.size(); i++)
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if (str[i] == '#' || str[i] == '=')
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str[i] = '?';
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if (sig.chunks.at(0).wire->width != 1)
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str += stringf("[%d]", sig.chunks.at(0).offset);
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cstr_buf.push_back(str);
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return cstr_buf.back().c_str();
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}
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void dump()
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{
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fprintf(f, "\n");
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fprintf(f, ".model %s\n", cstr(module->name));
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std::map<int, RTLIL::Wire*> inputs, outputs;
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for (auto &wire_it : module->wires) {
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RTLIL::Wire *wire = wire_it.second;
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if (wire->port_input)
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inputs[wire->port_id] = wire;
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if (wire->port_output)
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outputs[wire->port_id] = wire;
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}
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fprintf(f, ".inputs");
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for (auto &it : inputs) {
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RTLIL::Wire *wire = it.second;
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for (int i = 0; i < wire->width; i++)
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fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
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}
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fprintf(f, "\n");
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fprintf(f, ".outputs");
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for (auto &it : outputs) {
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RTLIL::Wire *wire = it.second;
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for (int i = 0; i < wire->width; i++)
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fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, 1, i)));
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}
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fprintf(f, "\n");
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fprintf(f, ".names $false\n");
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fprintf(f, ".names $true\n1\n");
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for (auto &cell_it : module->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == "$_INV_") {
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fprintf(f, ".names %s %s\n0 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\Y")));
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continue;
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}
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if (cell->type == "$_AND_") {
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fprintf(f, ".names %s %s %s\n11 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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continue;
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}
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if (cell->type == "$_OR_") {
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fprintf(f, ".names %s %s %s\n1- 1\n-1 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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continue;
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}
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if (cell->type == "$_XOR_") {
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fprintf(f, ".names %s %s %s\n10 1\n01 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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continue;
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}
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if (cell->type == "$_MUX_") {
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fprintf(f, ".names %s %s %s %s\n1-0 1\n-11 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")),
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cstr(cell->connections.at("\\S")), cstr(cell->connections.at("\\Y")));
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continue;
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}
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if (cell->type == "$_DFF_N_") {
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fprintf(f, ".latch %s %s fe %s\n",
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cstr(cell->connections.at("\\D")), cstr(cell->connections.at("\\Q")), cstr(cell->connections.at("\\C")));
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continue;
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}
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if (cell->type == "$_DFF_P_") {
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fprintf(f, ".latch %s %s re %s\n",
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cstr(cell->connections.at("\\D")), cstr(cell->connections.at("\\Q")), cstr(cell->connections.at("\\C")));
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continue;
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}
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fprintf(f, ".subckt %s", cstr(cell->type));
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for (auto &conn : cell->connections)
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for (int i = 0; i < conn.second.width; i++) {
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if (conn.second.width == 1)
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fprintf(f, " %s", cstr(conn.first));
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else
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fprintf(f, " %s[%d]", cstr(conn.first), i);
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fprintf(f, "=%s", cstr(conn.second.extract(i, 1)));
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}
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fprintf(f, "\n");
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}
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for (auto &conn : module->connections)
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for (int i = 0; i < conn.first.width; i++)
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fprintf(f, ".names %s %s\n1 1\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));
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fprintf(f, ".end\n");
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}
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static void dump(FILE *f, RTLIL::Module *module, RTLIL::Design *design)
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{
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BlifDumper dumper(f, module, design);
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dumper.dump();
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}
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};
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struct BlifBackend : public Backend {
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BlifBackend() : Backend("blif", "write design to BLIF file") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_blif [options] [filename]\n");
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log("\n");
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log("Write the current design to an BLIF file.\n");
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log("\n");
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log(" -top top_module\n");
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log(" set the specified module as design top module\n");
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log("\n");
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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std::string top_module_name;
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log_header("Executing BLIF backend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_module_name = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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std::vector<RTLIL::Module*> mod_list;
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for (auto module_it : design->modules)
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{
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RTLIL::Module *module = module_it.second;
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if ((module->attributes.count("\\placeholder") > 0) > 0)
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continue;
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if (module->processes.size() != 0)
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log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
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if (module->memories.size() != 0)
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log_error("Found munmapped emories in module %s: unmapped memories are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
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if (module->name == RTLIL::escape_id(top_module_name)) {
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BlifDumper::dump(f, module, design);
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top_module_name.clear();
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continue;
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}
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mod_list.push_back(module);
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}
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if (!top_module_name.empty())
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log_error("Can't find top module `%s'!\n", top_module_name.c_str());
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for (auto module : mod_list)
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BlifDumper::dump(f, module, design);
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}
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} BlifBackend;
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