mirror of https://github.com/YosysHQ/yosys.git
read_liberty: Defer handling of re-definitions
Postpone handling re-definitions to after we have established the cell is not supposed to be ignored on the grounds of one of the user-provided flags.
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@ -542,27 +542,13 @@ struct LibertyFrontend : public Frontend {
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if (cell->id != "cell" || cell->args.size() != 1)
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if (cell->id != "cell" || cell->args.size() != 1)
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continue;
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continue;
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std::string cell_name = RTLIL::escape_id(cell->args.at(0));
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if (design->has(cell_name)) {
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Module *existing_mod = design->module(cell_name);
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if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
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log_error("Re-definition of cell/module %s!\n", log_id(cell_name));
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} else if (flag_nooverwrite) {
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log("Ignoring re-definition of module %s.\n", log_id(cell_name));
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continue;
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} else {
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log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name));
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design->remove(existing_mod);
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}
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}
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// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
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// log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str());
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std::map<std::string, std::tuple<int, int, bool>> type_map = global_type_map;
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std::map<std::string, std::tuple<int, int, bool>> type_map = global_type_map;
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parse_type_map(type_map, cell);
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parse_type_map(type_map, cell);
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RTLIL::Module *module = new RTLIL::Module;
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RTLIL::Module *module = new RTLIL::Module;
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std::string cell_name = RTLIL::escape_id(cell->args.at(0));
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module->name = cell_name;
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module->name = cell_name;
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if (flag_lib)
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if (flag_lib)
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@ -747,6 +733,20 @@ struct LibertyFrontend : public Frontend {
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}
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}
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}
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}
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if (design->has(cell_name)) {
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Module *existing_mod = design->module(cell_name);
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if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
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log_error("Re-definition of cell/module %s!\n", log_id(cell_name));
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} else if (flag_nooverwrite) {
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log("Ignoring re-definition of module %s.\n", log_id(cell_name));
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delete module;
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goto skip_cell;
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} else {
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log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name));
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design->remove(existing_mod);
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}
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}
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module->fixup_ports();
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module->fixup_ports();
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design->add(module);
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design->add(module);
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cell_count++;
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cell_count++;
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