riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed parsing of module arguments when one type is used for many args

This commit is contained in:
Clifford Wolf 2013-11-19 20:35:31 +01:00
parent 63285b300c
commit 0dfdbd991a
1 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
frontends/verilog/parser.y
View File

@ -248,9 +248,16 @@ optional_comma:
module_arg:
TOK_ID range {
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
AstNode *node = ast_stack.back()->children.back()->clone();
node->str = *$1;
node->port_id = ++port_counter;
ast_stack.back()->children.push_back(node);
} else {
if (port_stubs.count(*$1) != 0)
frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
port_stubs[*$1] = ++port_counter;
}
if ($2 != NULL)
delete $2;
delete $1;