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Fixed parsing of module arguments when one type is used for many args

This commit is contained in:
Clifford Wolf 2013-11-19 20:35:31 +01:00
parent 63285b300c
commit 0dfdbd991a
1 changed files with 10 additions and 3 deletions
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7
frontends/verilog/parser.y
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@ -248,9 +248,16 @@ optional_comma:
module_arg: module_arg:
TOK_ID range { TOK_ID range {
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
AstNode *node = ast_stack.back()->children.back()->clone();
node->str = *$1;
node->port_id = ++port_counter;
ast_stack.back()->children.push_back(node);
} else {
if (port_stubs.count(*$1) != 0) if (port_stubs.count(*$1) != 0)
frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
port_stubs[*$1] = ++port_counter; port_stubs[*$1] = ++port_counter;
}
if ($2 != NULL) if ($2 != NULL)
delete $2; delete $2;
delete $1; delete $1;