From 2192873daa7915aa034e9afd1fe82efbc61320d1 Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Mon, 18 Mar 2013 19:26:35 +0100 Subject: [PATCH 1/8] added description of Makefile include files for build configuration --- README | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/README b/README index cbd77bb17..5da189473 100644 --- a/README +++ b/README @@ -40,14 +40,25 @@ or the 2-clause BSD license). Getting Started =============== -To build Yosys simply type 'make' in this directory. You need -a C++ compiler with C++11 support (up-to-date CLANG or GCC is -recommended) and some standard tools such as GNU Flex, GNU Bison, -and GNU Make. It might be necessary to make some changes to -the config section of the Makefile. The extensive tests require -Icarus Verilog. +You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is +recommended) and some standard tools such as GNU Flex, GNU Bison, and +GNU Make. The extensive tests require Icarus Verilog. + +To configure the build system to use a specific set of compiler and +build configuration, use one of + + $ make config-clang-debug + $ make config-gcc-debug + $ make config-release + +For other compilers and build configurations it might be +necessary to make some changes to the config section of the +Makefile. $ vi Makefile + +To build Yosys simply type 'make' in this directory. + $ make $ make test $ sudo make install From 15ad2db8fc4e608d05e87d4d447cb0a5f1081c95 Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Mon, 18 Mar 2013 20:58:47 +0100 Subject: [PATCH 2/8] fixed a crash when lines start with whitespace --- kernel/register.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/register.cc b/kernel/register.cc index ebb834c8f..a61548b64 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -132,7 +132,7 @@ void Pass::extra_args(std::vector args, size_t argidx, RTLIL::Desig void Pass::call(RTLIL::Design *design, std::string command) { std::vector args; - char *s = strdup(command.c_str()), *saveptr; + char *s = strdup(command.c_str()), *sstart = s, *saveptr; s += strspn(s, " \t\r\n"); if (*s == 0 || *s == '#') return; @@ -160,7 +160,7 @@ void Pass::call(RTLIL::Design *design, std::string command) } else args.push_back(str); } - free(s); + free(sstart); call(design, args); } From a4e2c887f12e6bf713ea77c7a2a687b3cd0b984a Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Mon, 18 Mar 2013 22:05:21 +0100 Subject: [PATCH 3/8] also optimize single-bit "$mux" cells in pass "opt_const", added suggestions for more optimizations --- passes/opt/opt_const.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 4d00807ab..909500967 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -113,7 +113,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1)); } - if (cell->type == "$_MUX_") { + if (cell->type == "$_MUX_" ||(cell->type == "$mux" && cell->parameters["\\WIDTH"].as_int() == 1)) { RTLIL::SigSpec input; input.append(cell->connections["\\S"]); input.append(cell->connections["\\B"]); @@ -125,6 +125,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1)); #ifdef MUX_UNDEF_SEL_TO_UNDEF_RESULTS if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1)); + // TODO: "0 " -> replace with "B AND S" gate + // TODO: " 1 " -> replace with "A OR S" gate + // TODO: "1 " -> replace with "B OR !S" gate + // TODO: " 0 " -> replace with "A AND !S" gate if (input.match(" *")) ACTION_DO_Y(x); #endif } From 69674652c5eafab7f96bcdab7618d57630ab0ae7 Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Mon, 18 Mar 2013 22:06:16 +0100 Subject: [PATCH 4/8] added one more suggestion to optimize MUXes in pass "opt_const" --- passes/opt/opt_const.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 909500967..5b87aeaa2 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -125,6 +125,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1)); #ifdef MUX_UNDEF_SEL_TO_UNDEF_RESULTS if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1)); + // TODO: "10 " -> replace with "!S" gate // TODO: "0 " -> replace with "B AND S" gate // TODO: " 1 " -> replace with "A OR S" gate // TODO: "1 " -> replace with "B OR !S" gate From 1d30c66a7f97cd522a87893c64ebe3a933f6b0ba Mon Sep 17 00:00:00 2001 From: Johann Glaser Date: Mon, 18 Mar 2013 22:06:53 +0100 Subject: [PATCH 5/8] added a TODO --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index 5da189473..97f2ba9b1 100644 --- a/README +++ b/README @@ -248,3 +248,5 @@ TODOs / Open Bugs - Better FSM state encoding +- For pass' "fsm_detect" help: add notes what criteria lets it detect an FSM + From b7fcf1fb9a7a6b4f84357d61bc4bb3c711511c7d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 19 Mar 2013 13:32:04 +0100 Subject: [PATCH 6/8] keep $mux and $_MUX_ optimizations separate in opt_const --- passes/opt/opt_const.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 5b87aeaa2..1e9b1331b 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -113,7 +113,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1)); } - if (cell->type == "$_MUX_" ||(cell->type == "$mux" && cell->parameters["\\WIDTH"].as_int() == 1)) { + if (cell->type == "$_MUX_") { RTLIL::SigSpec input; input.append(cell->connections["\\S"]); input.append(cell->connections["\\B"]); @@ -128,8 +128,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) // TODO: "10 " -> replace with "!S" gate // TODO: "0 " -> replace with "B AND S" gate // TODO: " 1 " -> replace with "A OR S" gate - // TODO: "1 " -> replace with "B OR !S" gate - // TODO: " 0 " -> replace with "A AND !S" gate + // TODO: "1 " -> replace with "B OR !S" gate (?) + // TODO: " 0 " -> replace with "A AND !S" gate (?) if (input.match(" *")) ACTION_DO_Y(x); #endif } From d8a7fa6b6771245b99af41783cbb3b8c0a12946a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 19 Mar 2013 13:32:39 +0100 Subject: [PATCH 7/8] improved $mux optimization in opt_const --- passes/opt/opt_const.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 1e9b1331b..aa376ae0e 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -242,11 +242,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) FOLD_1ARG_CELL(pos) FOLD_1ARG_CELL(neg) + // be very conservative with optimizing $mux cells as we do not want to break mux trees if (cell->type == "$mux") { - RTLIL::SigSpec input = cell->connections["\\S"]; - assign_map.apply(input); + RTLIL::SigSpec input = assign_map(cell->connections["\\S"]); + RTLIL::SigSpec inA = assign_map(cell->connections["\\A"]); + RTLIL::SigSpec inB = assign_map(cell->connections["\\B"]); if (input.is_fully_const()) ACTION_DO("\\Y", input.as_bool() ? cell->connections["\\B"] : cell->connections["\\A"]); + else if (inA == inB) + ACTION_DO("\\Y", cell->connections["\\A"]); } next_cell:; From 9f10acb84042ce0943c3b4d1234efa3899f0dff1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 19 Mar 2013 13:33:33 +0100 Subject: [PATCH 8/8] added optimizations for single-bit $eq/$ne with constant input to opt_const --- passes/opt/opt_const.cc | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index aa376ae0e..0effd964b 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -174,6 +174,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module) } } + if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 && + cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1) + { + RTLIL::SigSpec a = assign_map(cell->connections["\\A"]); + RTLIL::SigSpec b = assign_map(cell->connections["\\B"]); + + if (a.is_fully_const()) { + RTLIL::SigSpec tmp = a; + a = b, b = tmp; + } + + if (b.is_fully_const()) { + if (b.as_bool() == (cell->type == "$eq")) { + RTLIL::SigSpec input = b; + ACTION_DO("\\Y", cell->connections["\\A"]); + } else { + cell->type = "$not"; + cell->parameters.erase("\\B_WIDTH"); + cell->parameters.erase("\\B_SIGNED"); + cell->connections.erase("\\B"); + } + goto next_cell; + } + } + #define FOLD_1ARG_CELL(_t) \ if (cell->type == "$" #_t) { \ RTLIL::SigSpec a = cell->connections["\\A"]; \