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write_xaiger: cache arrival times

This commit is contained in:
Eddie Hung 2020-01-13 09:50:50 -08:00
parent 808b388e34
commit 0d2c06ee47
1 changed files with 17 additions and 11 deletions
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10
backends/aiger/xaiger.cc
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@ -184,6 +184,7 @@ struct XAigerWriter
} }
} }
dict<IdString,dict<IdString,int>> arrival_cache;
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type == "$_NOT_") if (cell->type == "$_NOT_")
{ {
@ -230,26 +231,31 @@ struct XAigerWriter
if (GetSize(box_list) <= abc9_box_seq) if (GetSize(box_list) <= abc9_box_seq)
box_list.resize(abc9_box_seq+1); box_list.resize(abc9_box_seq+1);
box_list[abc9_box_seq] = cell; box_list[abc9_box_seq] = cell;
// Only flop boxes may have arrival times
if (!inst_module->get_bool_attribute("\\abc9_flop")) if (!inst_module->get_bool_attribute("\\abc9_flop"))
continue; continue;
} }
auto &cell_arrivals = arrival_cache[cell->type];
for (const auto &conn : cell->connections()) { for (const auto &conn : cell->connections()) {
auto r = cell_arrivals.insert(conn.first);
auto &arrival = r.first->second;
if (r.second) {
auto port_wire = inst_module->wire(conn.first); auto port_wire = inst_module->wire(conn.first);
if (port_wire->port_output) { if (port_wire->port_output) {
int arrival = 0;
auto it = port_wire->attributes.find("\\abc9_arrival"); auto it = port_wire->attributes.find("\\abc9_arrival");
if (it != port_wire->attributes.end()) { if (it != port_wire->attributes.end()) {
if (it->second.flags != 0) if (it->second.flags != 0)
log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type)); log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
arrival = it->second.as_int(); arrival = it->second.as_int();
} }
}
}
if (arrival) if (arrival)
for (auto bit : sigmap(conn.second)) for (auto bit : sigmap(conn.second))
arrival_times[bit] = arrival; arrival_times[bit] = arrival;
} }
} }
}
bool cell_known = inst_module || cell->known(); bool cell_known = inst_module || cell->known();
for (const auto &c : cell->connections()) { for (const auto &c : cell->connections()) {