mirror of https://github.com/YosysHQ/yosys.git
Fix macc and mul tests
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parent
8246062acf
commit
0d1d8b4d24
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@ -300,6 +300,10 @@ code ffM clock sigM sigP
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reject;
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reject;
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clock = c;
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clock = c;
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}
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}
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// No enable mux possible without flop
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else if (ffMmux)
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reject;
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sigP = sigM;
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sigP = sigM;
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endcode
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endcode
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@ -341,8 +345,11 @@ endcode
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match ffPmux
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match ffPmux
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if param(dsp, \PREG).as_int() == 0
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if param(dsp, \PREG).as_int() == 0
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// new-value net must have exactly two users: dsp and ffP
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// If ffMmux, new-value net must have exactly three users: ffMmux, ffM and ffPmux
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if nusers(sigP) == 2
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if !ffMmux || nusers(sigP) == 3
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// Otherwise new-value net must have exactly two users: dsp and ffPmux
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if ffMmux || nusers(sigP) == 2
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select ffPmux->type.in($mux)
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select ffPmux->type.in($mux)
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// ffPmux output must have two users: ffPmux and ffP.D
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// ffPmux output must have two users: ffPmux and ffP.D
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select nusers(port(ffPmux, \Y)) == 2
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select nusers(port(ffPmux, \Y)) == 2
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@ -383,7 +390,11 @@ endmatch
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match ffP
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match ffP
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if !ffP_enable
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if !ffP_enable
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if param(dsp, \PREG).as_int() == 0
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if param(dsp, \PREG).as_int() == 0
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if nusers(sigP) == 2
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// If ffMmux, input net must have exactly three users: ffMmux, ffM and ffP
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if !ffMmux || nusers(sigP) == 3
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// Otherwise input net must have exactly two users: dsp and ffP
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if ffMmux || nusers(sigP) == 2
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select ffP->type.in($dff)
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select ffP->type.in($dff)
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// DSP48E1 does not support clock inversion
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// DSP48E1 does not support clock inversion
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select param(ffP, \CLK_POLARITY).as_bool()
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select param(ffP, \CLK_POLARITY).as_bool()
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@ -413,6 +424,9 @@ code ffP sigP clock
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sigP.replace(port(ffP, \D), port(ffP, \Q));
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sigP.replace(port(ffP, \D), port(ffP, \Q));
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}
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}
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// No enable mux possible without flop
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else if (ffPmux)
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reject;
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endcode
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endcode
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match postAddMux
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match postAddMux
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