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Work around DDR dout sim glitches in ice40 SB_IO sim model

This commit is contained in:
Clifford Wolf 2016-02-07 11:19:48 +01:00
parent e7bec9bbb8
commit 0ccfb88728
1 changed files with 7 additions and 1 deletions
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8
techlibs/ice40/cells_sim.v
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@ -47,11 +47,17 @@ module SB_IO (
din_1 = din_q_1; din_1 = din_q_1;
end end
// work around simulation glitches on dout in DDR mode
reg outclk_delayed_1;
reg outclk_delayed_2;
always @* outclk_delayed_1 <= OUTPUT_CLK;
always @* outclk_delayed_2 <= outclk_delayed_1;
always @* begin always @* begin
if (PIN_TYPE[3]) if (PIN_TYPE[3])
dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0; dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
else else
dout = (OUTPUT_CLK ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1; dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
end end
assign D_IN_0 = din_0, D_IN_1 = din_1; assign D_IN_0 = din_0, D_IN_1 = din_1;