riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed typo

This commit is contained in:
Andrew Zonenberg 2016-04-22 19:08:19 -07:00
parent ab11f2aa70
commit 0cbe70eaa4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/greenpak4/cells_sim.v
View File

@ -235,7 +235,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
reg[15:0] shreg = 0; reg[15:0] shreg = 0;
always @(posedge clk, negedge RSTN) begin always @(posedge clk, negedge nRST) begin
if(!nRST) if(!nRST)
shreg = 0; shreg = 0;