mirror of https://github.com/YosysHQ/yosys.git
Add -D DFF_MODE to abc9_map test
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@ -6,7 +6,7 @@ endmodule
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EOT
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EOT
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design -save gold
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design -save gold
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techmap -map +/xilinx/abc9_map.v -max_iter 1
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techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
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techmap -map +/xilinx/abc9_unmap.v
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techmap -map +/xilinx/abc9_unmap.v
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select -assert-count 1 t:FDSE
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select -assert-count 1 t:FDSE
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select -assert-count 1 t:FDSE_1
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select -assert-count 1 t:FDSE_1
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@ -29,7 +29,7 @@ endmodule
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EOT
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EOT
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design -save gold
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design -save gold
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techmap -map +/xilinx/abc9_map.v -max_iter 1
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techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
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techmap -map +/xilinx/abc9_unmap.v
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techmap -map +/xilinx/abc9_unmap.v
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:FDRE_1
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select -assert-count 1 t:FDRE_1
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@ -52,7 +52,7 @@ endmodule
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EOT
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EOT
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design -save gold
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design -save gold
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techmap -map +/xilinx/abc9_map.v -max_iter 1
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techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
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techmap -map +/xilinx/abc9_unmap.v
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techmap -map +/xilinx/abc9_unmap.v
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select -assert-count 1 t:FDCE
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select -assert-count 1 t:FDCE
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select -assert-count 1 t:FDCE_1
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select -assert-count 1 t:FDCE_1
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@ -76,7 +76,7 @@ endmodule
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EOT
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EOT
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design -save gold
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design -save gold
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techmap -map +/xilinx/abc9_map.v -max_iter 1
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techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE
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techmap -map +/xilinx/abc9_unmap.v
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techmap -map +/xilinx/abc9_unmap.v
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select -assert-count 1 t:FDPE
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select -assert-count 1 t:FDPE
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techmap -autoproc -map +/xilinx/cells_sim.v
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techmap -autoproc -map +/xilinx/cells_sim.v
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