mirror of https://github.com/YosysHQ/yosys.git
changes made to filenames + references
This commit is contained in:
C77874
parent
e5bdc9b5c9
commit
0bb7d1373f
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@ -37,14 +37,14 @@ $(eval $(call add_extra_objs,passes/pmgen/xilinx_dsp_cascade_pm.h))
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# --------------------------------------
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OBJS += passes/pmgen/mchp_dsp.o
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GENFILES += passes/pmgen/mchp_dsp_pm.h
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GENFILES += passes/pmgen/mchp_dsp_CREG_pm.h
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GENFILES += passes/pmgen/mchp_dsp_cascade_pm.h
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passes/pmgen/mchp_dsp.o: passes/pmgen/mchp_dsp_pm.h passes/pmgen/mchp_dsp_CREG_pm.h passes/pmgen/mchp_dsp_cascade_pm.h
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$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_pm.h))
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$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_CREG_pm.h))
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$(eval $(call add_extra_objs,passes/pmgen/mchp_dsp_cascade_pm.h))
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OBJS += passes/pmgen/microvhip.o
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GENFILES += passes/pmgen/microchip_dsp_pm.h
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GENFILES += passes/pmgen/microchip_dsp_CREG_pm.h
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GENFILES += passes/pmgen/microchip_dsp_cascade_pm.h
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passes/pmgen/microchip_dsp.o: passes/pmgen/microchip_dsp_pm.h passes/pmgen/microchip_dsp_CREG_pm.h passes/pmgen/microchip_dsp_cascade_pm.h
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$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_pm.h))
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$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_CREG_pm.h))
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$(eval $(call add_extra_objs,passes/pmgen/microchip_dsp_cascade_pm.h))
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# --------------------------------------
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@ -16,25 +16,25 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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#include <deque>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/mchp_dsp_pm.h"
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#include "passes/pmgen/mchp_dsp_CREG_pm.h"
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#include "passes/pmgen/mchp_dsp_cascade_pm.h"
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#include "passes/pmgen/microchip_dsp_CREG_pm.h"
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#include "passes/pmgen/microchip_dsp_cascade_pm.h"
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#include "passes/pmgen/microchip_dsp_pm.h"
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void mchp_dsp_pack(mchp_dsp_pm &pm)
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void microchip_dsp_pack(microchip_dsp_pm &pm)
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{
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auto &st = pm.st_mchp_dsp_pack;
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auto &st = pm.st_microchip_dsp_pack;
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log("Analysing %s.%s for MCHP MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
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log("Analysing %s.%s for Microchip MACC_PA packing.\n", log_id(pm.module), log_id(st.dsp));
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Cell *cell = st.dsp;
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//pack pre-adder
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// pack pre-adder
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if (st.preAdderStatic) {
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SigSpec &pasub = cell->connections_.at(ID(PASUB));
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log(" static PASUB preadder %s (%s)\n", log_id(st.preAdderStatic), log_id(st.preAdderStatic->type));
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@ -42,8 +42,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
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bool B_SIGNED = st.preAdderStatic->getParam(ID::A_SIGNED).as_bool();
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st.sigB.extend_u0(18, B_SIGNED);
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st.sigD.extend_u0(18, D_SIGNED);
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if (st.moveBtoA)
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{
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if (st.moveBtoA) {
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cell->setPort(ID::A, st.sigA); // if pre-adder feeds into A, original sigB will be moved to port A
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}
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cell->setPort(ID::B, st.sigB);
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@ -59,7 +58,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
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pm.autoremove(st.preAdderStatic);
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}
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//pack post-adder
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// pack post-adder
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if (st.postAdderStatic) {
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log(" postadder %s (%s)\n", log_id(st.postAdderStatic), log_id(st.postAdderStatic->type));
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SigSpec &sub = cell->connections_.at(ID(SUB));
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@ -79,18 +78,15 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
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cell->setPort(ID::C, st.sigC);
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}
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pm.autoremove(st.postAdderStatic);
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}
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// pack registers
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if (st.clock != SigBit())
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{
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if (st.clock != SigBit()) {
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cell->setPort(ID::CLK, st.clock);
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// function to absorb a register
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auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
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auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
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// input/output ports
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SigSpec D = ff->getPort(ID::D);
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SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
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@ -118,8 +114,7 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
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bool cepol = ff->getParam(ID::EN_POLARITY).as_bool();
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// enables are all active high
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cell->setPort(ceport, cepol ? ce : pm.module->Not(NEW_ID, ce));
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}
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else {
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} else {
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// enables are all active high
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cell->setPort(ceport, State::S1);
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}
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@ -127,12 +122,11 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
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// bypass set to 0
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cell->setPort(bypass, State::S0);
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for (auto c : Q.chunks()) {
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auto it = c.wire->attributes.find(ID::init);
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if (it == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset+c.width; i++) {
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for (int i = c.offset; i < c.offset + c.width; i++) {
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log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
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it->second[i] = State::Sx;
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}
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@ -189,29 +183,27 @@ void mchp_dsp_pack(mchp_dsp_pm &pm)
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SigSpec P = st.sigP;
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if (GetSize(P) < 48)
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P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
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P.append(pm.module->addWire(NEW_ID, 48 - GetSize(P)));
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cell->setPort(ID::P, P);
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pm.blacklist(cell);
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}
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// For packing cascaded DSPs
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void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
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void microchip_dsp_packC(microchip_dsp_CREG_pm &pm)
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{
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auto &st = pm.st_mchp_dsp_packC;
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auto &st = pm.st_microchip_dsp_packC;
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log_debug("Analysing %s.%s for MCHP DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
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log_debug("Analysing %s.%s for Microchip DSP packing (REG_C).\n", log_id(pm.module), log_id(st.dsp));
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log_debug("ffC: %s\n", log_id(st.ffC, "--"));
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Cell *cell = st.dsp;
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if (st.clock != SigBit())
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{
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if (st.clock != SigBit()) {
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cell->setPort(ID::CLK, st.clock);
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// same function as above, used for the last CREG we need to absorb
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auto f = [&pm,cell](SigSpec &A, Cell* ff, IdString ceport, IdString rstport, IdString bypass) {
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auto f = [&pm, cell](SigSpec &A, Cell *ff, IdString ceport, IdString rstport, IdString bypass) {
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// input/output ports
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SigSpec D = ff->getPort(ID::D);
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SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
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@ -246,12 +238,11 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
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// bypass set to 0
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cell->setPort(bypass, State::S0);
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for (auto c : Q.chunks()) {
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auto it = c.wire->attributes.find(ID::init);
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if (it == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset+c.width; i++) {
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for (int i = c.offset; i < c.offset + c.width; i++) {
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log_assert(it->second[i] == State::S0 || it->second[i] == State::Sx);
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it->second[i] = State::Sx;
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}
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@ -280,17 +271,17 @@ void mchp_dsp_packC(mchp_dsp_CREG_pm &pm)
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pm.blacklist(cell);
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}
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struct MchpDspPass : public Pass {
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MchpDspPass() : Pass("mchp_dsp", "MCHP: pack resources into DSPs") { }
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struct MicrochipDspPass : public Pass {
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MicrochipDspPass() : Pass("microchip_dsp", "MICROCHIP: pack resources into DSPs") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" mchp_dsp [options] [selection]\n");
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log(" microchip_dsp [options] [selection]\n");
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log("\n");
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log("Pack input registers 'A', 'B', 'C', and 'D' (with optional enable/reset),\n");
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log("output register 'P' (with optional enable/reset), pre-adder and/or post-adder into\n");
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log("MCHP DSP resources.\n");
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log("Microchip DSP resources.\n");
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log("\n");
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log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
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log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
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@ -303,24 +294,23 @@ struct MchpDspPass : public Pass {
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log("implement wide multipliers). Cascade chains are limited to a mazimum length \n");
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log("of 24 cells, corresponding to PolarFire (pf) devices.\n");
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log("\n");
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log("This pass is a no-op if the scratchpad variable 'mchp_dsp.multonly' is set\n");
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log("This pass is a no-op if the scratchpad variable 'microchip_dsp.multonly' is set\n");
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log("to 1.\n");
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log("\n");
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log("\n");
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log(" -family {pf}\n");
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log(" -family {polarfire}\n");
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log(" select the family to target\n");
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log(" default: pf\n");
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log(" default: polarfire\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing MCHP_DSP pass (pack resources into DSPs).\n");
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log_header(design, "Executing MICROCHIP_DSP pass (pack resources into DSPs).\n");
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std::string family = "pf";
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std::string family = "polarfire";
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if ((args[argidx] == "-family") && argidx+1 < args.size()) {
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for (argidx = 1; argidx < args.size(); argidx++) {
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if ((args[argidx] == "-family") && argidx + 1 < args.size()) {
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family = args[++argidx];
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continue;
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}
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@ -330,7 +320,7 @@ struct MchpDspPass : public Pass {
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for (auto module : design->selected_modules()) {
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if (design->scratchpad_get_bool("mchp_dsp.multonly"))
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if (design->scratchpad_get_bool("microchip_dsp.multonly"))
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continue;
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{
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@ -343,8 +333,8 @@ struct MchpDspPass : public Pass {
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// check for an accumulator pattern based on whether
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// a post-adder and PREG are both present AND
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// if PREG feeds into this post-adder.
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mchp_dsp_pm pm(module, module->selected_cells());
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pm.run_mchp_dsp_pack(mchp_dsp_pack);
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microchip_dsp_pm pm(module, module->selected_cells());
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pm.run_microchip_dsp_pack(microchip_dsp_pack);
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}
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// Separating out CREG packing is necessary since there
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@ -356,18 +346,17 @@ struct MchpDspPass : public Pass {
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// PREG of an upstream DSP that had not been visited
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// yet
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{
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mchp_dsp_CREG_pm pm(module, module->selected_cells());
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pm.run_mchp_dsp_packC(mchp_dsp_packC);
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microchip_dsp_CREG_pm pm(module, module->selected_cells());
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pm.run_microchip_dsp_packC(microchip_dsp_packC);
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}
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// Lastly, identify and utilise PCOUT -> PCIN chains
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{
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mchp_dsp_cascade_pm pm(module, module->selected_cells());
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pm.run_mchp_dsp_cascade();
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microchip_dsp_cascade_pm pm(module, module->selected_cells());
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pm.run_microchip_dsp_cascade();
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}
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}
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}
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} MchpDspPass;
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} MicrochipDspPass;
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PRIVATE_NAMESPACE_END
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@ -16,7 +16,7 @@
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// This file describes the main pattern matcher setup (of three total) that
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// forms the `mchp_dsp` pass described in mchp_dsp.cc
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// forms the `microchip_dsp` pass described in microchip_dsp.cc
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// At a high level, it works as follows:
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// ( 1) Starting from a DSP cell. Capture DSP configurations as states
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// ( 2) Match for pre-adder
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@ -31,7 +31,7 @@
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// |MULT|------ | adder | +----+
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// +----+ \-------/
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pattern mchp_dsp_pack
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pattern microchip_dsp_pack
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigP
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@ -16,7 +16,7 @@
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// This file describes the second of three pattern matcher setups that
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// forms the `mchp_dsp` pass described in mchp_dsp.cc
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// forms the `microchip_dsp` pass described in microchip_dsp.cc
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// At a high level, it works as follows:
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// (1) Starting from a DSP cell that (a) doesn't have a CREG already,
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// and (b) uses the 'C' port
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@ -24,21 +24,21 @@
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using a subpattern discussed below)
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// Notes:
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// - Running CREG packing after mchp_dsp_pack is necessary since there is no
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// - Running CREG packing after microchip_dsp_pack is necessary since there is no
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// guarantee that the cell ordering corresponds to the "expected" case (i.e.
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// the order in which they appear in the source) thus the possiblity existed
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// where a register got packed as a CREG into a downstream DSP, while it should
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// have otherwise been a PREG of an upstream DSP that had not been visited.
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// yet.
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// - The reason this is separated out from the mchp_dsp.pmg file is
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// - The reason this is separated out from the microchip_dsp.pmg file is
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// for efficiency --- each *.pmg file creates a class of the same basename,
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// which when constructed, creates a custom database tailored to the
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// pattern(s) contained within. Since the pattern in this file must be
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// executed after the pattern contained in mchp_dsp.pmg, it is necessary
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// executed after the pattern contained in microchip_dsp.pmg, it is necessary
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// to reconstruct this database. Separating the two patterns into
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// independent files causes two smaller, more specific, databases.
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pattern mchp_dsp_packC
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pattern microchip_dsp_packC
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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@ -16,7 +16,7 @@
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// This file describes the third of three pattern matcher setups that
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// forms the `mchp_dsp` pass described in mchp_dsp.cc
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// forms the `microchip_dsp` pass described in microchip_dsp.cc
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// At a high level, it works as follows:
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// (1) Starting from a DSP cell that
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// (a) CDIN_FDBK_SEL is set to default "00"
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@ -32,7 +32,7 @@
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// height of a DSP column) with each DSP in each chunk being rewritten
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// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
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pattern mchp_dsp_cascade
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pattern microchip_dsp_cascade
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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udata <vector<std::tuple<Cell*,int>>> chain longest_chain
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@ -16,16 +16,16 @@
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OBJS += techlibs/mchp/synth_mchp.o
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OBJS += techlibs/mchp/mchp_dffopt.o
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OBJS += techlibs/microchip/synth_microchip.o
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OBJS += techlibs/microchip/microchip_dffopt.o
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/arith_map.v))
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_map.v))
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/cells_sim.v))
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/pf_dsp_map.v))
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$(eval $(call add_share_file,share/microchip,techlibs/microchip/arith_map.v))
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$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_map.v))
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$(eval $(call add_share_file,share/microchip,techlibs/microchip/cells_sim.v))
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$(eval $(call add_share_file,share/microchip,techlibs/microchip/pf_dsp_map.v))
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/brams_defs.vh))
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM_map.v))
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/LSRAM.txt))
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$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM_map.v))
|
||||
$(eval $(call add_share_file,share/mchp,techlibs/mchp/uSRAM.txt))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/brams_defs.vh))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM_map.v))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/LSRAM.txt))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM_map.v))
|
||||
$(eval $(call add_share_file,share/microchip,techlibs/microchip/uSRAM.txt))
|
||||
|
|
@ -21,7 +21,7 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|||
|
||||
|
||||
(* techmap_celltype = "$_MUX4_" *)
|
||||
module \$__mchp_MUX4_ (A, B, C, D, S, T, Y);
|
||||
module \$__microchip_MUX4_ (A, B, C, D, S, T, Y);
|
||||
input A, B, C, D, S, T;
|
||||
output Y;
|
||||
MX4 _TECHMAP_REPLACE_.MUX4(.D3(D), .D2(C), .D1(B), .D0(A), .S1(T), .S0(S), .Y(Y));
|
||||
|
|
@ -30,7 +30,7 @@ endmodule
|
|||
|
||||
|
||||
(* techmap_celltype = "$reduce_xor" *)
|
||||
module \$__mchp_XOR8_ (A, Y);
|
||||
module \$__microchip_XOR8_ (A, Y);
|
||||
parameter A_SIGNED = 0;
|
||||
parameter A_WIDTH = 0;
|
||||
parameter Y_WIDTH = 0;
|
||||
|
|
@ -28,11 +28,11 @@ endmodule
|
|||
// for sync set/reset registers, we can pass them into ABC9. So we need to follow the simplification idiom
|
||||
// and map to intermediate cell types
|
||||
module \$_SDFFCE_PN0P_ (input D, C, R, E, output Q);
|
||||
MCHP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
|
||||
MICROCHIP_SYNC_RESET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Reset(R), .En(E), .Q(Q));
|
||||
endmodule
|
||||
|
||||
module \$_SDFFCE_PN1P_ (input D, C, R, E, output Q);
|
||||
MCHP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
|
||||
MICROCHIP_SYNC_SET_DFF _TECHMAP_REPLACE_ (.D(D), .CLK(C), .Set(R), .En(E), .Q(Q));
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ endmodule
|
|||
|
||||
// map intermediate flops to SLE
|
||||
`ifdef FINAL_MAP
|
||||
module MCHP_SYNC_SET_DFF(
|
||||
module MICROCHIP_SYNC_SET_DFF(
|
||||
input D,
|
||||
input CLK,
|
||||
input Set,
|
||||
|
|
@ -61,7 +61,7 @@ module MCHP_SYNC_SET_DFF(
|
|||
SLE _TECHMAP_REPLACE_ (.D(D), .CLK(CLK), .EN(En), .ALn(1'b1), .ADn(1'b0), .SLn(Set), .SD(1'b1), .LAT(1'b0), .Q(Q));
|
||||
endmodule
|
||||
|
||||
module MCHP_SYNC_RESET_DFF(
|
||||
module MICROCHIP_SYNC_RESET_DFF(
|
||||
input D,
|
||||
input CLK,
|
||||
input Reset,
|
||||
|
|
@ -155,11 +155,11 @@ endmodule
|
|||
|
||||
// sequential elements
|
||||
|
||||
// MCHP_SYNC_SET_DFF and MCHP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
|
||||
// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
|
||||
// see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module MCHP_SYNC_SET_DFF(
|
||||
module MICROCHIP_SYNC_SET_DFF(
|
||||
input D,
|
||||
input CLK,
|
||||
input Set,
|
||||
|
|
@ -185,7 +185,7 @@ module MCHP_SYNC_SET_DFF(
|
|||
endmodule
|
||||
|
||||
(* abc9_flop, lib_whitebox *)
|
||||
module MCHP_SYNC_RESET_DFF(
|
||||
module MICROCHIP_SYNC_RESET_DFF(
|
||||
input D,
|
||||
input CLK,
|
||||
input Reset,
|
||||
|
|
@ -16,8 +16,8 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|||
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include "kernel/yosys.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
|
@ -25,7 +25,8 @@ PRIVATE_NAMESPACE_BEGIN
|
|||
typedef std::pair<Const, std::vector<SigBit>> LutData;
|
||||
|
||||
// Compute a LUT implementing (select ^ select_inv) ? alt_data : data. Returns true if successful.
|
||||
bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size) {
|
||||
bool merge_lut(LutData &result, const LutData &data, const LutData select, bool select_inv, SigBit alt_data, int max_lut_size)
|
||||
{
|
||||
// First, gather input signals -- insert new signals at the beginning
|
||||
// of the vector, so they don't disturb the likely-critical D LUT input
|
||||
// timings.
|
||||
|
|
@ -97,13 +98,13 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
|
|||
return true;
|
||||
}
|
||||
|
||||
struct MchpDffOptPass : public Pass {
|
||||
MchpDffOptPass() : Pass("mchp_dffopt", "MCHP: optimize FF control signal usage") { }
|
||||
struct MicrochipDffOptPass : public Pass {
|
||||
MicrochipDffOptPass() : Pass("microchip_dffopt", "MICROCHIP: optimize FF control signal usage") {}
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" mchp_dffopt [options] [selection]\n");
|
||||
log(" microchip_dffopt [options] [selection]\n");
|
||||
log("\n");
|
||||
log("Converts hardware clock enable and set/reset signals on FFs to emulation\n");
|
||||
log("using LUTs, if doing so would improve area. Operates on post-techmap LUT, DFF\n");
|
||||
|
|
@ -112,15 +113,14 @@ struct MchpDffOptPass : public Pass {
|
|||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing MCHP_DFFOPT pass (optimize FF control signal usage).\n");
|
||||
log_header(design, "Executing MICROCHIP_DFFOPT pass (optimize FF control signal usage).\n");
|
||||
|
||||
size_t argidx;
|
||||
int max_lut_size = 4;
|
||||
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
for (auto module : design->selected_modules()) {
|
||||
log("Optimizing FFs in %s.\n", log_id(module));
|
||||
|
||||
SigMap sigmap(module);
|
||||
|
|
@ -128,8 +128,7 @@ struct MchpDffOptPass : public Pass {
|
|||
dict<SigBit, int> bit_uses;
|
||||
|
||||
// Gather LUTs.
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
for (auto cell : module->selected_cells()) {
|
||||
for (auto port : cell->connections())
|
||||
for (auto bit : port.second)
|
||||
bit_uses[sigmap(bit)]++;
|
||||
|
|
@ -154,7 +153,7 @@ struct MchpDffOptPass : public Pass {
|
|||
goto lut_sigin_done;
|
||||
sigin.push_back(sigmap(cell->getPort(ID(D))));
|
||||
|
||||
lut_sigin_done:
|
||||
lut_sigin_done:
|
||||
bit_to_lut[sigout] = make_pair(LutData(init, sigin), cell);
|
||||
}
|
||||
}
|
||||
|
|
@ -164,8 +163,7 @@ lut_sigin_done:
|
|||
bit_uses[sigmap(SigBit(wire, i))]++;
|
||||
|
||||
// Iterate through FFs.
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
for (auto cell : module->selected_cells()) {
|
||||
|
||||
if (!cell->type.in(ID(SLE))) // not a SLE
|
||||
continue;
|
||||
|
|
@ -176,7 +174,6 @@ lut_sigin_done:
|
|||
if (!cell->getPort(ID(ALn)).is_fully_ones()) // async FF
|
||||
continue;
|
||||
|
||||
|
||||
const bool hasSyncLoad = cell->getPort(ID(SLn)).is_wire();
|
||||
const bool has_s = hasSyncLoad && cell->getPort(ID(SD)).is_fully_ones();
|
||||
const bool has_r = hasSyncLoad && cell->getPort(ID(SD)).is_fully_zero();
|
||||
|
|
@ -196,7 +193,6 @@ lut_sigin_done:
|
|||
LutData lut_d = it_D->second.first;
|
||||
Cell *cell_d = it_D->second.second;
|
||||
|
||||
|
||||
LutData lut_d_post_ce;
|
||||
LutData lut_d_post_s;
|
||||
LutData lut_d_post_r;
|
||||
|
|
@ -216,7 +212,8 @@ lut_sigin_done:
|
|||
if (!merge_lut(lut_d_post_ce, lut_d, lut_ce, true, sig_Q, max_lut_size))
|
||||
continue;
|
||||
|
||||
// If this gets rid of a CE LUT, it's worth it. If not, it still may be worth it, if we can remove set/reset as well.
|
||||
// If this gets rid of a CE LUT, it's worth it. If not, it still may be worth it, if we can remove set/reset
|
||||
// as well.
|
||||
if (it_CE != bit_to_lut.end())
|
||||
worthy_post_ce = true;
|
||||
} else if (sig_CE.data != State::S1) {
|
||||
|
|
@ -231,7 +228,7 @@ lut_sigin_done:
|
|||
if (has_s) {
|
||||
SigBit sig_S = sigmap(cell->getPort(ID(SLn)));
|
||||
LutData lut_s = LutData(Const(2, 2), {sig_S}); // INIT = 10
|
||||
bool inv_s = true; // active low
|
||||
bool inv_s = true; // active low
|
||||
auto it_S = bit_to_lut.find(sig_S);
|
||||
if (it_S != bit_to_lut.end())
|
||||
lut_s = it_S->second.first;
|
||||
|
|
@ -253,7 +250,7 @@ lut_sigin_done:
|
|||
if (has_r) {
|
||||
SigBit sig_R = sigmap(cell->getPort(ID(SLn)));
|
||||
LutData lut_r = LutData(Const(2, 2), {sig_R}); // INIT = 10
|
||||
bool inv_r = true; // active low
|
||||
bool inv_r = true; // active low
|
||||
auto it_R = bit_to_lut.find(sig_R);
|
||||
if (it_R != bit_to_lut.end())
|
||||
lut_r = it_R->second.first;
|
||||
|
|
@ -270,7 +267,7 @@ lut_sigin_done:
|
|||
}
|
||||
}
|
||||
|
||||
unmap:
|
||||
unmap:
|
||||
|
||||
// SLE cannot have both synchronous set and reset implemented at the same time
|
||||
log_assert(!(worthy_post_r && worthy_post_s));
|
||||
|
|
@ -288,10 +285,14 @@ unmap:
|
|||
}
|
||||
|
||||
std::string ports;
|
||||
if (worthy_post_r) ports += " + R";
|
||||
if (worthy_post_s) ports += " + S";
|
||||
if (worthy_post_ce) ports += " + CE";
|
||||
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire), GetSize(lut_d.second), GetSize(final_lut.second));
|
||||
if (worthy_post_r)
|
||||
ports += " + R";
|
||||
if (worthy_post_s)
|
||||
ports += " + S";
|
||||
if (worthy_post_ce)
|
||||
ports += " + CE";
|
||||
log(" Merging D%s LUTs for %s/%s (%d -> %d)\n", ports.c_str(), log_id(cell), log_id(sig_Q.wire),
|
||||
GetSize(lut_d.second), GetSize(final_lut.second));
|
||||
|
||||
// Okay, we're doing it. Unmap ports.
|
||||
if ((has_s && worthy_post_s) || worthy_post_r) {
|
||||
|
|
@ -304,20 +305,20 @@ unmap:
|
|||
// Create the new LUT.
|
||||
Cell *lut_cell = nullptr;
|
||||
switch (GetSize(final_lut.second)) {
|
||||
case 1:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG1));
|
||||
break;
|
||||
case 2:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG2));
|
||||
break;
|
||||
case 3:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG3));
|
||||
break;
|
||||
case 4:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG4));
|
||||
break;
|
||||
default:
|
||||
log_assert(!"unknown lut size");
|
||||
case 1:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG1));
|
||||
break;
|
||||
case 2:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG2));
|
||||
break;
|
||||
case 3:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG3));
|
||||
break;
|
||||
case 4:
|
||||
lut_cell = module->addCell(NEW_ID, ID(CFG4));
|
||||
break;
|
||||
default:
|
||||
log_assert(!"unknown lut size");
|
||||
}
|
||||
lut_cell->attributes = cell_d->attributes;
|
||||
Wire *lut_out = module->addWire(NEW_ID);
|
||||
|
|
@ -334,7 +335,6 @@ unmap:
|
|||
}
|
||||
}
|
||||
}
|
||||
} MchpDffOptPass;
|
||||
} MicrochipDffOptPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
||||
|
|
@ -16,23 +16,22 @@ ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|||
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "kernel/rtlil.h"
|
||||
#include "kernel/log.h"
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/rtlil.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct SynthMchpPass : public ScriptPass
|
||||
{
|
||||
SynthMchpPass() : ScriptPass("synth_mchp", "synthesis for Microchip FPGAs") { }
|
||||
struct SynthMicrochipPass : public ScriptPass {
|
||||
SynthMicrochipPass() : ScriptPass("synth_microchip", "synthesis for Microchip FPGAs") {}
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" synth_mchp [options]\n");
|
||||
log(" synth_microchip [options]\n");
|
||||
log("\n");
|
||||
log("This command runs synthesis for Microchip FPGAs. Operating on\n");
|
||||
log("partly selected designs is not supported (you must submit a fully-selected \n");
|
||||
|
|
@ -137,30 +136,29 @@ struct SynthMchpPass : public ScriptPass
|
|||
clear_flags();
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-top" && argidx + 1 < args.size()) {
|
||||
top_opt = "-top " + args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
|
||||
if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx + 1 < args.size()) {
|
||||
family = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
|
||||
if (args[argidx] == "-edif" && argidx + 1 < args.size()) {
|
||||
edif_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-blif" && argidx+1 < args.size()) {
|
||||
if (args[argidx] == "-blif" && argidx + 1 < args.size()) {
|
||||
blif_file = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-run" && argidx+1 < args.size()) {
|
||||
size_t pos = args[argidx+1].find(':');
|
||||
if (args[argidx] == "-run" && argidx + 1 < args.size()) {
|
||||
size_t pos = args[argidx + 1].find(':');
|
||||
if (pos == std::string::npos)
|
||||
break;
|
||||
run_from = args[++argidx].substr(0, pos);
|
||||
run_to = args[argidx].substr(pos+1);
|
||||
run_to = args[argidx].substr(pos + 1);
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-flatten") {
|
||||
|
|
@ -231,7 +229,7 @@ struct SynthMchpPass : public ScriptPass
|
|||
lut_size = 4;
|
||||
} else {
|
||||
log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family.c_str());
|
||||
}
|
||||
}
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
|
|
@ -239,8 +237,7 @@ struct SynthMchpPass : public ScriptPass
|
|||
if (abc9 && retime)
|
||||
log_cmd_error("-retime option not currently compatible with -abc9!\n");
|
||||
|
||||
|
||||
log_header(design, "Executing SYNTH_MCHP pass.\n");
|
||||
log_header(design, "Executing SYNTH_MICROCHIP pass.\n");
|
||||
log_push();
|
||||
|
||||
run_script(design, run_from, run_to);
|
||||
|
|
@ -256,7 +253,7 @@ struct SynthMchpPass : public ScriptPass
|
|||
|
||||
if (check_label("begin")) {
|
||||
std::string read_args;
|
||||
read_args += " -lib -specify +/mchp/cells_sim.v";
|
||||
read_args += " -lib -specify +/microchip/cells_sim.v";
|
||||
run("read_verilog" + read_args);
|
||||
|
||||
run(stringf("hierarchy -check %s", top_opt.c_str()));
|
||||
|
|
@ -286,18 +283,18 @@ struct SynthMchpPass : public ScriptPass
|
|||
|
||||
if (check_label("map_dsp", "(skip if '-nodsp')")) {
|
||||
if (!nodsp || help_mode) {
|
||||
run("memory_dff"); // mchp_dsp will merge registers, reserve memory port registers first
|
||||
run("memory_dff"); // microchip_dsp will merge registers, reserve memory port registers first
|
||||
if (help_mode)
|
||||
run("techmap -map +/mul2dsp.v -map +/mchp/{family}_dsp_map.v {options}");
|
||||
run("techmap -map +/mul2dsp.v -map +/microchip/{family}_dsp_map.v {options}");
|
||||
else if (family == "pf") // Microchip - map multipliers to DSP
|
||||
run("techmap -map +/mul2dsp.v -map +/mchp/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
|
||||
// limited to 18x18 in order to take
|
||||
// advantage of the (PCOUT >> 17) -> PCIN
|
||||
// dedicated cascade chain capability
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 "
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
|
||||
run("techmap -map +/mul2dsp.v -map +/microchip/pf_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 "
|
||||
"-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally
|
||||
// limited to 18x18 in order to take
|
||||
// advantage of the (PCOUT >> 17) -> PCIN
|
||||
// dedicated cascade chain capability
|
||||
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
|
||||
"-D DSP_Y_MINWIDTH=9 "
|
||||
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18");
|
||||
|
||||
run("select a:mul2dsp");
|
||||
run("setattr -unset mul2dsp");
|
||||
|
|
@ -305,9 +302,9 @@ struct SynthMchpPass : public ScriptPass
|
|||
run("wreduce");
|
||||
run("select -clear");
|
||||
if (help_mode)
|
||||
run("mchp_dsp -family <family>");
|
||||
run("microchip_dsp -family <family>");
|
||||
else if (family == "pf") // Microchip - absorb cells into DSP
|
||||
run("mchp_dsp -family " + family);
|
||||
run("microchip_dsp -family " + family);
|
||||
|
||||
run("chtype -set $mul t:$__soft_mul");
|
||||
}
|
||||
|
|
@ -324,9 +321,10 @@ struct SynthMchpPass : public ScriptPass
|
|||
|
||||
if (check_label("map_memory")) {
|
||||
std::string params = "";
|
||||
std::string LSRAM_map = "+/mchp/LSRAM_map.v";
|
||||
std::string uSRAM_map = "+/mchp/uSRAM_map.v";
|
||||
if (debug_memory) run("write_verilog -noexpr memory_map_pre.vm");
|
||||
std::string LSRAM_map = "+/microchip/LSRAM_map.v";
|
||||
std::string uSRAM_map = "+/microchip/uSRAM_map.v";
|
||||
if (debug_memory)
|
||||
run("write_verilog -noexpr memory_map_pre.vm");
|
||||
if (help_mode) {
|
||||
params = " [...]";
|
||||
} else {
|
||||
|
|
@ -335,30 +333,32 @@ struct SynthMchpPass : public ScriptPass
|
|||
// cost of a single bit for memory lowered to soft logic
|
||||
params += " -logic-cost-rom 0.015625";
|
||||
|
||||
params += " -lib +/mchp/LSRAM.txt";
|
||||
params += " -lib +/mchp/uSRAM.txt";
|
||||
LSRAM_map = "+/mchp/LSRAM_map.v";
|
||||
uSRAM_map = "+/mchp/uSRAM_map.v";
|
||||
params += " -lib +/microchip/LSRAM.txt";
|
||||
params += " -lib +/microchip/uSRAM.txt";
|
||||
LSRAM_map = "+/microchip/LSRAM_map.v";
|
||||
uSRAM_map = "+/microchip/uSRAM_map.v";
|
||||
}
|
||||
if (nobram) params += " -no-auto-block";
|
||||
if (nobram)
|
||||
params += " -no-auto-block";
|
||||
}
|
||||
|
||||
// transform memories into intermediate cells
|
||||
// Cost based transformation. The cost is assigned by us for each cell.
|
||||
run("memory_libmap" + params);
|
||||
if (debug_memory) run("write_verilog -noexpr memory_map_libmap.vm");
|
||||
if (debug_memory)
|
||||
run("write_verilog -noexpr memory_map_libmap.vm");
|
||||
|
||||
// map intermediate cells to actual RAM macros
|
||||
// NOTE: order doesnt matter here
|
||||
run("techmap -map " + LSRAM_map);
|
||||
run("techmap -map " + uSRAM_map);
|
||||
if (debug_memory) run("write_verilog -noexpr memory_map_final.vm");
|
||||
if (debug_memory)
|
||||
run("write_verilog -noexpr memory_map_final.vm");
|
||||
}
|
||||
|
||||
if (check_label("map_ffram")) {
|
||||
run("opt -fast -full");
|
||||
|
||||
|
||||
// blast unmapped RAM to flops or LUTs
|
||||
run("memory_map");
|
||||
}
|
||||
|
|
@ -366,7 +366,8 @@ struct SynthMchpPass : public ScriptPass
|
|||
if (check_label("fine")) {
|
||||
run("opt -full");
|
||||
|
||||
if (debug_carry) run("write_verilog -noexpr ARI1_cells.vm");
|
||||
if (debug_carry)
|
||||
run("write_verilog -noexpr ARI1_cells.vm");
|
||||
|
||||
if (!nocarry) {
|
||||
// converts $mux -> $_MUX_ to allow muxcover to work
|
||||
|
|
@ -376,21 +377,24 @@ struct SynthMchpPass : public ScriptPass
|
|||
run("simplemap t:$xor"); // only mapping reduce_xor
|
||||
|
||||
// mapping based on Yosys internal gates
|
||||
if (debug_carry) run("write_verilog -noexpr ARI1_pre.vm");
|
||||
if (debug_carry)
|
||||
run("write_verilog -noexpr ARI1_pre.vm");
|
||||
|
||||
// collapse $_AND_/$_OR_/$_XOR_ chains into reduction cells
|
||||
run("extract_reduce");
|
||||
|
||||
if (debug_carry) run("write_verilog -noexpr ARI1_extract_reduce.vm");
|
||||
if (debug_carry)
|
||||
run("write_verilog -noexpr ARI1_extract_reduce.vm");
|
||||
|
||||
// pack mux trees into $_MUX4_
|
||||
run("muxcover -nodecode -mux4=220");
|
||||
|
||||
if (debug_carry) run("write_verilog -noexpr ARI1_muxcover.vm");
|
||||
|
||||
run("techmap -map +/mchp/arith_map.v");
|
||||
if (debug_carry) run("write_verilog -noexpr ARI1_post.vm");
|
||||
if (debug_carry)
|
||||
run("write_verilog -noexpr ARI1_muxcover.vm");
|
||||
|
||||
run("techmap -map +/microchip/arith_map.v");
|
||||
if (debug_carry)
|
||||
run("write_verilog -noexpr ARI1_post.vm");
|
||||
}
|
||||
|
||||
// convert all remaining cells to gates
|
||||
|
|
@ -403,10 +407,11 @@ struct SynthMchpPass : public ScriptPass
|
|||
// Needs to be done before logic optimization, so that inverters (inserted
|
||||
// here because of negative-polarity output enable) are handled.
|
||||
if (help_mode || !noiopad) {
|
||||
run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD", "(unless -noiobs)");
|
||||
run("iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD",
|
||||
"(unless -noiobs)");
|
||||
}
|
||||
|
||||
std::string techmap_args = "-map +/techmap.v -map +/mchp/cells_map.v";
|
||||
std::string techmap_args = "-map +/techmap.v -map +/microchip/cells_map.v";
|
||||
run("techmap " + techmap_args);
|
||||
run("clean");
|
||||
}
|
||||
|
|
@ -447,11 +452,9 @@ struct SynthMchpPass : public ScriptPass
|
|||
// $_DLATCH_[NP][NP][01]_ (D-latch + reset to 0/1)
|
||||
// $_DLATCHSR_[NP][NP][NP]_ (D-latch + set + reset)
|
||||
|
||||
|
||||
if (family == "pf") {
|
||||
std::string params = "";
|
||||
|
||||
|
||||
// D-flop with async reset and enable
|
||||
// posedge CLK, active low reset to 1 or 0, active high EN
|
||||
params += " -cell $_DFFE_PN?P_ 01";
|
||||
|
|
@ -467,11 +470,10 @@ struct SynthMchpPass : public ScriptPass
|
|||
run("dfflegalize" + params, "(Converts FFs to supported types)");
|
||||
}
|
||||
|
||||
|
||||
if (abc9 || help_mode) {
|
||||
if (dff || help_mode)
|
||||
run("zinit -all w:* t:$_SDFFCE_*", "('-dff' only)");
|
||||
run("techmap -D NO_LUT -map +/mchp/cells_map.v", "('-abc9' only)");
|
||||
run("techmap -D NO_LUT -map +/microchip/cells_map.v", "('-abc9' only)");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -493,8 +495,7 @@ struct SynthMchpPass : public ScriptPass
|
|||
if (dff)
|
||||
abc9_opts += " -dff";
|
||||
run("abc9" + abc9_opts);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
std::string abc_opts = " -lut " + lut_size_s;
|
||||
if (dff)
|
||||
abc_opts += " -dff";
|
||||
|
|
@ -505,21 +506,18 @@ struct SynthMchpPass : public ScriptPass
|
|||
run("clean");
|
||||
|
||||
if (help_mode || !abc9)
|
||||
run("techmap -D NO_LUT -map +/mchp/cells_map.v", "(only if not '-abc9')");
|
||||
std::string techmap_args = "-map +/mchp/cells_map.v -D FINAL_MAP";
|
||||
run("techmap -D NO_LUT -map +/microchip/cells_map.v", "(only if not '-abc9')");
|
||||
std::string techmap_args = "-map +/microchip/cells_map.v -D FINAL_MAP";
|
||||
techmap_args += " -D LUT_WIDTH=" + lut_size_s;
|
||||
run("techmap " + techmap_args);
|
||||
|
||||
if (help_mode || lut_size == 4)
|
||||
run("mchp_dffopt");
|
||||
|
||||
|
||||
run("microchip_dffopt");
|
||||
}
|
||||
|
||||
run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
|
||||
|
||||
run("clean -purge");
|
||||
run("clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD");
|
||||
|
||||
run("clean -purge");
|
||||
|
||||
if (check_label("check")) {
|
||||
run("hierarchy -check");
|
||||
|
|
@ -538,6 +536,6 @@ struct SynthMchpPass : public ScriptPass
|
|||
run(stringf("write_blif %s", blif_file.c_str()));
|
||||
}
|
||||
}
|
||||
} SynthMchpPass;
|
||||
} SynthMicrochipPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -17,7 +17,7 @@
|
|||
# read verilog files
|
||||
read_verilog Registers.v
|
||||
|
||||
synth_mchp -top Registers -abc9 -family pf -noiopad
|
||||
synth_microchip -top Registers -abc9 -family polarfire -noiopad
|
||||
|
||||
# write final outputfile
|
||||
write_verilog -noexpr Registers.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog carryout.v
|
||||
|
||||
synth_mchp -top carryout -abc9 -family pf -noiopad
|
||||
synth_microchip -top carryout -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr carryout.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog cascade.v
|
||||
|
||||
synth_mchp -top cascade -abc9 -family pf -noiopad
|
||||
synth_microchip -top cascade -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr cascade.vm
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
read_verilog dff_opt.v
|
||||
|
||||
synth_mchp -top dff_opt -abc9 -family pf -noiopad
|
||||
synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
|
||||
|
||||
# write final outputfile
|
||||
write_verilog -noexpr dff_opt.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog full_dsp.v
|
||||
|
||||
synth_mchp -top full_dsp -abc9 -family pf -noiopad
|
||||
synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr full_dsp.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog large_mult.v
|
||||
|
||||
synth_mchp -top large_mult -abc9 -family pf -noiopad
|
||||
synth_microchip -top large_mult -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr large_mult.vm
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
read_verilog mac.v
|
||||
|
||||
# run the synth flow, specifies top module and additional parameters
|
||||
synth_mchp -top mac -abc9 -family pf -noiopad
|
||||
synticrochip -top mac -abc9 -family polarfire -noiopad
|
||||
|
||||
# write final outputfile
|
||||
write_verilog -noexpr mac.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog postAdd_mult.v
|
||||
|
||||
synth_mchp -top postAdd_mult -abc9 -family pf -noiopad
|
||||
synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr postAdd_mult.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog post_adder.v
|
||||
|
||||
synth_mchp -top post_adder -abc9 -family pf
|
||||
synth_microchip -top post_adder -abc9 -family polarfire
|
||||
|
||||
write_verilog -noexpr post_adder.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog pre_adder_dsp.v
|
||||
|
||||
synth_mchp -top pre_adder_dsp -abc9 -family pf -noiopad
|
||||
synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr pre_adder_dsp.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog ram_SDP.v
|
||||
|
||||
synth_mchp -top ram_SDP -abc9 -family pf -noiopad
|
||||
synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr ram_SDP.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog ram_TDP.v
|
||||
|
||||
synth_mchp -top ram_TDP -abc9 -family pf -noiopad -debug_memory
|
||||
synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
|
||||
|
||||
write_verilog -noexpr ram_TDP.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog reduce.v
|
||||
|
||||
synth_mchp -top reduce -abc9 -family pf -noiopad
|
||||
synth_microchip -top reduce -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr reduce.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog reg_c.v
|
||||
|
||||
synth_mchp -top reg_c -abc9 -family pf -noiopad
|
||||
synth_microchip -top reg_c -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr reg_c.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog reg_test.v
|
||||
|
||||
synth_mchp -top reg_test -abc9 -family pf -noiopad
|
||||
synth_microchip -top reg_test -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr reg_test.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog signed_mult.v
|
||||
|
||||
synth_mchp -top signed_mult -abc9 -family pf -noiopad
|
||||
synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr signed_mult.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog simple_ram.v
|
||||
|
||||
synth_mchp -top simple_ram -abc9 -family pf -noiopad
|
||||
synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr simple_ram.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog unsigned_mult.v
|
||||
|
||||
synth_mchp -top unsigned_mult -abc9 -family pf -noiopad
|
||||
synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr unsigned_mult.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog uram_ar.v
|
||||
|
||||
synth_mchp -top uram_ar -abc9 -family pf -noiopad
|
||||
synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr uram_ar.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog uram_sr.v
|
||||
|
||||
synth_mchp -top uram_sr -abc9 -family pf -noiopad
|
||||
synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr uram_sr.vm
|
||||
|
|
@ -16,6 +16,6 @@
|
|||
|
||||
read_verilog widemux.v
|
||||
|
||||
synth_mchp -top widemux -abc9 -family pf -noiopad
|
||||
synth_microchip -top widemux -abc9 -family polarfire -noiopad
|
||||
|
||||
write_verilog -noexpr widemux.vm
|
||||
Loading…
Reference in New Issue