mirror of https://github.com/YosysHQ/yosys.git
Fixed build with gcc-4.6
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c55eb8f8a6
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0b8b8d41eb
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@ -20,7 +20,7 @@ Update the CHANGELOG file:
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vi CHANGELOG
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Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.7,release}":
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Run all tests with "make config-{clang-debug,gcc-debug,gcc-4.6,release}":
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cd ~yosys
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make clean
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12
Makefile
12
Makefile
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@ -1,7 +1,7 @@
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CONFIG := clang
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# CONFIG := gcc
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# CONFIG := gcc-4.7
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# CONFIG := gcc-4.6
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# features (the more the better)
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ENABLE_TCL := 1
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@ -67,8 +67,8 @@ CXX = gcc
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CXXFLAGS += -std=gnu++0x -Os
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endif
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ifeq ($(CONFIG),gcc-4.7)
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CXX = gcc-4.7
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ifeq ($(CONFIG),gcc-4.6)
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CXX = gcc-4.6
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CXXFLAGS += -std=gnu++0x -Os
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endif
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@ -282,8 +282,8 @@ config-clang: clean
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config-gcc: clean
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echo 'CONFIG := gcc' > Makefile.conf
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config-gcc-4.7: clean
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echo 'CONFIG := gcc-4.7' > Makefile.conf
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config-gcc-4.6: clean
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echo 'CONFIG := gcc-4.6' > Makefile.conf
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config-gprof: clean
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echo 'CONFIG := gcc' > Makefile.conf
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@ -300,5 +300,5 @@ config-sudo:
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-include techlibs/*/*.d
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.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator
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.PHONY: config-clean config-clang config-gcc config-gcc-4.7 config-gprof config-sudo
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.PHONY: config-clean config-clang config-gcc config-gcc-4.6 config-gprof config-sudo
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@ -102,7 +102,7 @@ struct ModIndex : public RTLIL::Monitor
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auto_reload_module = false;
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}
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virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override
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virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) OVERRIDE
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{
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if (auto_reload_module)
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reload_module();
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@ -77,7 +77,7 @@ struct Frontend : Pass
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Frontend(std::string name, std::string short_help = "** document me **");
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virtual void run_register();
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virtual ~Frontend();
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) override final;
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) OVERRIDE FINAL;
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
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static std::vector<std::string> next_args;
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@ -93,7 +93,7 @@ struct Backend : Pass
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Backend(std::string name, std::string short_help = "** document me **");
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virtual void run_register();
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virtual ~Backend();
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) override final;
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) OVERRIDE FINAL;
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
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void extra_args(FILE *&f, std::string &filename, std::vector<std::string> args, size_t argidx);
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@ -64,6 +64,14 @@
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# define USING_YOSYS_NAMESPACE
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#endif
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#if __cplusplus >= 201103L
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# define OVERRIDE override
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# define FINAL final
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#else
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# define OVERRIDE
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# define FINAL
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#endif
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YOSYS_NAMESPACE_BEGIN
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namespace RTLIL {
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@ -24,34 +24,34 @@ PRIVATE_NAMESPACE_BEGIN
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struct TraceMonitor : public RTLIL::Monitor
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{
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virtual void notify_module_add(RTLIL::Module *module) override
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virtual void notify_module_add(RTLIL::Module *module) OVERRIDE
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{
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log("#TRACE# Module add: %s\n", log_id(module));
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}
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virtual void notify_module_del(RTLIL::Module *module) override
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virtual void notify_module_del(RTLIL::Module *module) OVERRIDE
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{
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log("#TRACE# Module delete: %s\n", log_id(module));
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}
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virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override
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virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) OVERRIDE
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{
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log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
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}
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virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override
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virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) OVERRIDE
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{
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log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
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}
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virtual void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) override
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virtual void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) OVERRIDE
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{
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log("#TRACE# New connections in module %s:\n", log_id(module));
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for (auto &sigsig : sigsig_vec)
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log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
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}
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virtual void notify_blackout(RTLIL::Module *module) override
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virtual void notify_blackout(RTLIL::Module *module) OVERRIDE
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{
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log("#TRACE# Blackout in module %s:\n", log_id(module));
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}
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