mirror of https://github.com/YosysHQ/yosys.git
Added "wreduce" command (work in progress)
This commit is contained in:
Clifford Wolf
parent
653edd7a2f
commit
0b02f6ca30
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@ -20,4 +20,5 @@ OBJS += passes/cmds/write_file.o
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OBJS += passes/cmds/connwrappers.o
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OBJS += passes/cmds/cover.o
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OBJS += passes/cmds/trace.o
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OBJS += passes/cmds/wreduce.o
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@ -0,0 +1,252 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include <type_traits>
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USING_YOSYS_NAMESPACE
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using namespace RTLIL;
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PRIVATE_NAMESPACE_BEGIN
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struct WreduceConfig
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{
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std::set<IdString> supported_cell_types;
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WreduceConfig()
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{
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supported_cell_types.insert("$not");
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supported_cell_types.insert("$pos");
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supported_cell_types.insert("$bu0");
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supported_cell_types.insert("$neg");
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supported_cell_types.insert("$and");
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supported_cell_types.insert("$or");
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supported_cell_types.insert("$xor");
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supported_cell_types.insert("$xnor");
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supported_cell_types.insert("$shl");
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supported_cell_types.insert("$shr");
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supported_cell_types.insert("$sshl");
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supported_cell_types.insert("$sshr");
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supported_cell_types.insert("$shift");
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supported_cell_types.insert("$shiftx");
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supported_cell_types.insert("$lt");
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supported_cell_types.insert("$le");
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supported_cell_types.insert("$eq");
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supported_cell_types.insert("$ne");
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supported_cell_types.insert("$eqx");
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supported_cell_types.insert("$nex");
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supported_cell_types.insert("$ge");
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supported_cell_types.insert("$gt");
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supported_cell_types.insert("$add");
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supported_cell_types.insert("$sub");
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// supported_cell_types.insert("$mul");
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// supported_cell_types.insert("$div");
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// supported_cell_types.insert("$mod");
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// supported_cell_types.insert("$pow");
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// supported_cell_types.insert("$mux");
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// supported_cell_types.insert("$pmux");
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// supported_cell_types.insert("$safe_pmux");
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}
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};
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struct WreduceWorker
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{
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WreduceConfig *config;
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Module *module;
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ModIndex mi;
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std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells;
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std::set<SigBit> work_queue_bits;
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SigMap constmap;
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WreduceWorker(WreduceConfig *config, Module *module) :
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config(config), module(module), mi(module) { }
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void run_reduce_inport(Cell *cell, char port)
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{
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bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
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SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port)));
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int bits_removed = 0;
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if (is_signed) {
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while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == constmap(sig[SIZE(sig)-2]))
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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} else {
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while (SIZE(sig) > 1 && constmap(sig[SIZE(sig)-1]) == S0)
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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}
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if (bits_removed) {
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log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
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bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort(stringf("\\%c", port), sig);
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}
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}
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void run_cell(Cell *cell)
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{
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if (config->supported_cell_types.count(cell->type) == 0)
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return;
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if (cell->type == ID("$shl") || cell->type == ID("$shr") || cell->type == ID("$sshl") || cell->type == ID("$sshr"))
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cell->setParam("\\B_SIGNED", false);
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if (cell->hasParam("\\A_SIGNED"))
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run_reduce_inport(cell, 'A');
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if (cell->hasParam("\\B_SIGNED"))
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run_reduce_inport(cell, 'B');
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SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
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int bits_removed = 0;
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while (SIZE(sig) > 0) {
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auto info = mi.query(sig[SIZE(sig)-1]);
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if (info->is_output || SIZE(info->ports) > 1)
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break;
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sig.remove(SIZE(sig)-1);
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bits_removed++;
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}
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if (cell->type == ID("$not") || cell->type == ID("$pos") || cell->type == ID("$bu0") || cell->type == ID("$neg") ||
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cell->type == ID("$and") || cell->type == ID("$or") || cell->type == ID("$xor") || cell->type == ID("$xnor") ||
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cell->type == ID("$add") || cell->type == ID("$sub") || cell->type == ID("$mul"))
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{
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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int a_size = 0, b_size = 0;
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if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A"));
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if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B"));
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while (SIZE(sig) > 1 && SIZE(sig) > std::max(a_size, b_size)) {
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module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0);
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sig.remove(SIZE(sig)-1);
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bits_removed++;
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}
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}
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if (bits_removed) {
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log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
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bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort("\\Y", sig);
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}
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cell->fixup_parameters();
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}
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void run()
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{
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for (auto c : module->selected_cells())
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work_queue_cells.insert(c);
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while (!work_queue_cells.empty())
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{
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work_queue_bits.clear();
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for (auto c : work_queue_cells)
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run_cell(c);
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work_queue_cells.clear();
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for (auto bit : work_queue_bits)
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for (auto port : mi.query_ports(bit))
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work_queue_cells.insert(port.cell);
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}
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std::set<SigBit> removed_wire_bits;
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for (auto w : module->selected_wires())
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{
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int bits_removed = 0;
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while (w->width > 0) {
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SigBit bit(w, w->width-1);
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auto info = mi.query(bit);
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if (info == nullptr || (!info->is_output && !info->is_input && !SIZE(info->ports))) {
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removed_wire_bits.insert(bit);
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bits_removed++;
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w->width--;
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continue;
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}
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break;
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}
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if (bits_removed)
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log("Removed top %d bits (of %d) from wire %s.%s.\n",
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bits_removed, SIZE(w) + bits_removed, log_id(module), log_id(w));
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}
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if (!removed_wire_bits.empty()) {
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std::vector<RTLIL::SigSig> new_conn = module->connections();
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for (auto &ss : new_conn) {
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SigSig new_ss;
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for (int i = 0; i < SIZE(ss.first); i++)
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if (!removed_wire_bits.count(ss.first[i]) && !removed_wire_bits.count(ss.second[i])) {
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new_ss.first.append_bit(ss.first[i]);
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new_ss.second.append_bit(ss.second[i]);
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}
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ss = std::move(new_ss);
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}
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module->new_connections(new_conn);
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}
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}
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};
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struct WreducePass : public Pass {
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WreducePass() : Pass("wreduce", "reduce the word size of operations is possible") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" wreduce [options] [selection]\n");
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log("\n");
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log("This command reduces the word size of operations.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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WreduceConfig config;
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log_header("Executing WREDCUE pass (reducing word size of cells).\n");
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log_error("FIXME: This command is under construction.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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if (module->has_processes_warn())
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continue;
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WreduceWorker worker(&config, module);
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worker.run();
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}
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}
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} WreducePass;
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PRIVATE_NAMESPACE_END
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