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Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx
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commit
0aeb6105eb
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@ -2011,6 +2011,28 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
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Instance *inst = net->Driver();
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Instance *inst = net->Driver();
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// Detect condition expression in sva_at_only mode
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if (sva_at_only)
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do {
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Instance *inst_mux = net->Driver();
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if (inst_mux->Type() != PRIM_MUX)
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break;
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bool pwr1 = inst_mux->GetInput1()->IsPwr();
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bool pwr2 = inst_mux->GetInput2()->IsPwr();
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if (!pwr1 && !pwr2)
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break;
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Net *sva_net = pwr1 ? inst_mux->GetInput2() : inst_mux->GetInput1();
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if (!verific_is_sva_net(importer, sva_net))
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break;
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inst = sva_net->Driver();
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cond_net = inst_mux->GetControl();
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cond_pol = pwr1;
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} while (0);
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if (inst != nullptr && inst->Type() == PRIM_SVA_AT)
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if (inst != nullptr && inst->Type() == PRIM_SVA_AT)
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{
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{
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net = inst->GetInput1();
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net = inst->GetInput1();
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@ -1598,13 +1598,18 @@ struct VerificSvaImporter
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if (inst == nullptr)
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if (inst == nullptr)
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{
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{
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log_assert(trig == State::S1);
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if (trig != State::S1) {
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if (accept_p != nullptr)
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*accept_p = module->And(NEW_ID, trig, importer->net_map_at(net));
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if (reject_p != nullptr)
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*reject_p = module->And(NEW_ID, trig, module->Not(NEW_ID, importer->net_map_at(net)));
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} else {
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if (accept_p != nullptr)
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if (accept_p != nullptr)
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*accept_p = importer->net_map_at(net);
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*accept_p = importer->net_map_at(net);
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if (reject_p != nullptr)
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if (reject_p != nullptr)
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*reject_p = module->Not(NEW_ID, importer->net_map_at(net));
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*reject_p = module->Not(NEW_ID, importer->net_map_at(net));
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}
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}
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}
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else
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else
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if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
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if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
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inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
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inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
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