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solves #675

This commit is contained in:
rafaeltp 2018-10-20 17:50:21 -07:00
parent f25d0de6f8
commit 0ad4321781
2 changed files with 21 additions and 11 deletions
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4
kernel/rtlil.h
View File

@ -1304,6 +1304,10 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
}
inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
if(sig.size() != 1 || sig.chunks().size() != 1) {
std::cout << "rtp " << sig.size() << std::endl;
std::cout << "rtp " << sig.chunks().size() << std::endl;
}
log_assert(sig.size() == 1 && sig.chunks().size() == 1);
*this = SigBit(sig.chunks().front());
}

16
passes/equiv/equiv_make.cc
View File

@ -297,15 +297,21 @@ struct EquivMakeWorker
SigSpec old_sig = assign_map(conn.second);
SigSpec new_sig = rd_signal_map(old_sig);
if(old_sig != new_sig) {
for(auto & old_bit : old_sig.bits()) {
SigBit new_bit = new_sig.bits()[old_bit.offset];
visited_cells.clear();
if (old_sig != new_sig) {
if (check_signal_in_fanout(visited_cells, old_sig, new_sig))
if (old_bit != new_bit) {
if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
continue;
log("Changing input %s of cell %s (%s): %s -> %s\n",
log_id(conn.first), log_id(c), log_id(c->type),
log_signal(old_sig), log_signal(new_sig));
c->setPort(conn.first, new_sig);
log_signal(old_bit), log_signal(new_bit));
c->setPort(conn.first, new_bit);
}
}
}
}
@ -412,7 +418,7 @@ struct EquivMakeWorker
}
}
bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigSpec source_bit, SigSpec target_bit)
{
if (source_bit == target_bit)
return true;